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[PATCH v5 06/20] qtest: make read/write operation appear to be from CPU
From: |
Alex Bennée |
Subject: |
[PATCH v5 06/20] qtest: make read/write operation appear to be from CPU |
Date: |
Fri, 11 Nov 2022 18:25:21 +0000 |
The point of qtest is to simulate how running code might interact with
the system. However because it's not a real system we have places in
the code which especially handle check qtest_enabled() before
referencing current_cpu. Now we can encode these details in the
MemTxAttrs lets do that so we can start removing them.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
---
v2
- use a common macro instead of specific MEMTXATTRS_QTEST
v3
- macro moved to earlier patch
---
softmmu/qtest.c | 26 +++++++++++++-------------
1 file changed, 13 insertions(+), 13 deletions(-)
diff --git a/softmmu/qtest.c b/softmmu/qtest.c
index d3e0ab4eda..5e9ac234ce 100644
--- a/softmmu/qtest.c
+++ b/softmmu/qtest.c
@@ -520,22 +520,22 @@ static void qtest_process_command(CharBackend *chr, gchar
**words)
if (words[0][5] == 'b') {
uint8_t data = value;
- address_space_write(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED,
+ address_space_write(first_cpu->as, addr, MEMTXATTRS_CPU(first_cpu),
&data, 1);
} else if (words[0][5] == 'w') {
uint16_t data = value;
tswap16s(&data);
- address_space_write(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED,
+ address_space_write(first_cpu->as, addr, MEMTXATTRS_CPU(first_cpu),
&data, 2);
} else if (words[0][5] == 'l') {
uint32_t data = value;
tswap32s(&data);
- address_space_write(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED,
+ address_space_write(first_cpu->as, addr, MEMTXATTRS_CPU(first_cpu),
&data, 4);
} else if (words[0][5] == 'q') {
uint64_t data = value;
tswap64s(&data);
- address_space_write(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED,
+ address_space_write(first_cpu->as, addr, MEMTXATTRS_CPU(first_cpu),
&data, 8);
}
qtest_send_prefix(chr);
@@ -554,21 +554,21 @@ static void qtest_process_command(CharBackend *chr, gchar
**words)
if (words[0][4] == 'b') {
uint8_t data;
- address_space_read(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED,
+ address_space_read(first_cpu->as, addr, MEMTXATTRS_CPU(first_cpu),
&data, 1);
value = data;
} else if (words[0][4] == 'w') {
uint16_t data;
- address_space_read(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED,
+ address_space_read(first_cpu->as, addr, MEMTXATTRS_CPU(first_cpu),
&data, 2);
value = tswap16(data);
} else if (words[0][4] == 'l') {
uint32_t data;
- address_space_read(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED,
+ address_space_read(first_cpu->as, addr, MEMTXATTRS_CPU(first_cpu),
&data, 4);
value = tswap32(data);
} else if (words[0][4] == 'q') {
- address_space_read(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED,
+ address_space_read(first_cpu->as, addr, MEMTXATTRS_CPU(first_cpu),
&value, 8);
tswap64s(&value);
}
@@ -589,7 +589,7 @@ static void qtest_process_command(CharBackend *chr, gchar
**words)
g_assert(len);
data = g_malloc(len);
- address_space_read(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, data,
+ address_space_read(first_cpu->as, addr, MEMTXATTRS_CPU(first_cpu),
data,
len);
enc = g_malloc(2 * len + 1);
@@ -615,7 +615,7 @@ static void qtest_process_command(CharBackend *chr, gchar
**words)
g_assert(ret == 0);
data = g_malloc(len);
- address_space_read(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, data,
+ address_space_read(first_cpu->as, addr, MEMTXATTRS_CPU(first_cpu),
data,
len);
b64_data = g_base64_encode(data, len);
qtest_send_prefix(chr);
@@ -650,7 +650,7 @@ static void qtest_process_command(CharBackend *chr, gchar
**words)
data[i] = 0;
}
}
- address_space_write(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, data,
+ address_space_write(first_cpu->as, addr, MEMTXATTRS_CPU(first_cpu),
data,
len);
g_free(data);
@@ -673,7 +673,7 @@ static void qtest_process_command(CharBackend *chr, gchar
**words)
if (len) {
data = g_malloc(len);
memset(data, pattern, len);
- address_space_write(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED,
+ address_space_write(first_cpu->as, addr, MEMTXATTRS_CPU(first_cpu),
data, len);
g_free(data);
}
@@ -707,7 +707,7 @@ static void qtest_process_command(CharBackend *chr, gchar
**words)
out_len = MIN(out_len, len);
}
- address_space_write(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, data,
+ address_space_write(first_cpu->as, addr, MEMTXATTRS_CPU(first_cpu),
data,
len);
qtest_send_prefix(chr);
--
2.34.1
- Re: [PATCH v5 02/20] target/arm: ensure TCG IO accesses set appropriate MemTxAttrs, (continued)
- [PATCH v5 01/20] hw: encode accessing CPU index in MemTxAttrs, Alex Bennée, 2022/11/11
- [PATCH v5 15/20] hw/i386: update vapic_write to use MemTxAttrs, Alex Bennée, 2022/11/11
- [PATCH v5 19/20] hw/isa: derive CPUState from MemTxAttrs in apm_ioport_writeb, Alex Bennée, 2022/11/11
- [PATCH v5 06/20] qtest: make read/write operation appear to be from CPU,
Alex Bennée <=
- [PATCH v5 09/20] hw/arm: remove current_cpu hack from pxa2xx access, Alex Bennée, 2022/11/11
- [PATCH v5 10/20] target/microblaze: initialise MemTxAttrs for CPU access, Alex Bennée, 2022/11/11
- [PATCH v5 12/20] target/riscv: initialise MemTxAttrs for CPU access, Alex Bennée, 2022/11/11
- [PATCH v5 16/20] include: add MEMTXATTRS_MACHINE helper, Alex Bennée, 2022/11/11