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[PULL 13/49] target/mips: Add missing default cases for some nanoMIPS po
From: |
Philippe Mathieu-Daudé |
Subject: |
[PULL 13/49] target/mips: Add missing default cases for some nanoMIPS pools |
Date: |
Sat, 11 Jun 2022 12:32:36 +0200 |
From: Stefan Pejic <stefan.pejic@syrmia.com>
Switch statements for the code segments that handle nanoMIPS
instruction pools P.LL, P.SC, P.SHIFT, P.LS.S1, P.LS.E0, PP.LSXS
do not have proper default case, resulting in not generating
reserved instruction exception for certain illegal opcodes.
Fix this by adding default cases for these switch statements that
trigger reserved instruction exception.
Signed-off-by: Stefan Pejic <stefan.pejic@syrmia.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20220504110403.613168-7-stefan.pejic@syrmia.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/tcg/nanomips_translate.c.inc | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/target/mips/tcg/nanomips_translate.c.inc
b/target/mips/tcg/nanomips_translate.c.inc
index 1ee5c8c8d4..c0ba2bf1b1 100644
--- a/target/mips/tcg/nanomips_translate.c.inc
+++ b/target/mips/tcg/nanomips_translate.c.inc
@@ -2707,6 +2707,9 @@ static void gen_p_lsx(DisasContext *ctx, int rd, int rs,
int rt)
case NM_SDC1XS:
tcg_gen_shli_tl(t0, t0, 3);
break;
+ default:
+ gen_reserved_instruction(ctx);
+ goto out;
}
}
gen_op_addr_add(ctx, t0, t0, t1);
@@ -2797,6 +2800,7 @@ static void gen_p_lsx(DisasContext *ctx, int rd, int rs,
int rt)
break;
}
+out:
tcg_temp_free(t0);
tcg_temp_free(t1);
}
@@ -3944,6 +3948,9 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env,
DisasContext *ctx)
gen_shift_imm(ctx, OPC_ROTR, rt, rs,
extract32(ctx->opcode, 0, 5));
break;
+ default:
+ gen_reserved_instruction(ctx);
+ break;
}
}
break;
@@ -4245,6 +4252,9 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env,
DisasContext *ctx)
check_xnp(ctx);
gen_llwp(ctx, rs, 0, rt, extract32(ctx->opcode, 3, 5));
break;
+ default:
+ gen_reserved_instruction(ctx);
+ break;
}
break;
case NM_P_SC:
@@ -4257,6 +4267,9 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env,
DisasContext *ctx)
gen_scwp(ctx, rs, 0, rt, extract32(ctx->opcode, 3, 5),
false);
break;
+ default:
+ gen_reserved_instruction(ctx);
+ break;
}
break;
case NM_CACHE:
@@ -4265,6 +4278,9 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env,
DisasContext *ctx)
gen_cache_operation(ctx, rt, rs, s);
}
break;
+ default:
+ gen_reserved_instruction(ctx);
+ break;
}
break;
case NM_P_LS_E0:
@@ -4371,6 +4387,9 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env,
DisasContext *ctx)
break;
}
break;
+ default:
+ gen_reserved_instruction(ctx);
+ break;
}
break;
case NM_P_LS_WM:
--
2.36.1
- [PULL 03/49] target/mips: Fix df_extract_val() and df_extract_df() dfe lookup, (continued)
- [PULL 03/49] target/mips: Fix df_extract_val() and df_extract_df() dfe lookup, Philippe Mathieu-Daudé, 2022/06/11
- [PULL 04/49] target/mips: Fix msa checking condition in trans_msa_elm_fn(), Philippe Mathieu-Daudé, 2022/06/11
- [PULL 05/49] target/mips: Do not treat msa INSERT as NOP when wd is zero, Philippe Mathieu-Daudé, 2022/06/11
- [PULL 06/49] target/mips: Fix store adress of high 64bit in helper_msa_st_b(), Philippe Mathieu-Daudé, 2022/06/11
- [PULL 07/49] target/mips: Fix FTRUNC_S and FTRUNC_U trans helper, Philippe Mathieu-Daudé, 2022/06/11
- [PULL 08/49] target/mips: Fix emulation of nanoMIPS MTHLIP instruction, Philippe Mathieu-Daudé, 2022/06/11
- [PULL 09/49] target/mips: Fix emulation of nanoMIPS EXTRV_S.H instruction, Philippe Mathieu-Daudé, 2022/06/11
- [PULL 10/49] target/mips: Fix emulation of nanoMIPS BPOSGE32C instruction, Philippe Mathieu-Daudé, 2022/06/11
- [PULL 11/49] target/mips: Fix emulation of nanoMIPS BNEC[32] instruction, Philippe Mathieu-Daudé, 2022/06/11
- [PULL 12/49] target/mips: Fix handling of unaligned memory access for nanoMIPS ISA, Philippe Mathieu-Daudé, 2022/06/11
- [PULL 13/49] target/mips: Add missing default cases for some nanoMIPS pools,
Philippe Mathieu-Daudé <=
- [PULL 14/49] target/mips: Undeprecate nanoMIPS ISA support in QEMU, Philippe Mathieu-Daudé, 2022/06/11
- [PULL 15/49] hw/block/fdc-sysbus: Always mark sysbus floppy controllers as not having DMA, Philippe Mathieu-Daudé, 2022/06/11
- [PULL 16/49] hw/acpi/piix4: move xen_enabled() logic from piix4_pm_init() to piix4_pm_realize(), Philippe Mathieu-Daudé, 2022/06/11
- [PULL 17/49] hw/acpi/piix4: change smm_enabled from int to bool, Philippe Mathieu-Daudé, 2022/06/11
- [PULL 18/49] hw/acpi/piix4: convert smm_enabled bool to qdev property, Philippe Mathieu-Daudé, 2022/06/11
- [PULL 19/49] hw/acpi/piix4: move PIIX4PMState into separate piix4.h header, Philippe Mathieu-Daudé, 2022/06/11
- [PULL 20/49] hw/acpi/piix4: alter piix4_pm_init() to return PIIX4PMState, Philippe Mathieu-Daudé, 2022/06/11
- [PULL 21/49] hw/acpi/piix4: rename piix4_pm_init() to piix4_pm_initfn(), Philippe Mathieu-Daudé, 2022/06/11
- [PULL 22/49] hw/acpi/piix4: use qdev gpio to wire up sci_irq, Philippe Mathieu-Daudé, 2022/06/11
- [PULL 24/49] hw/i386/pc_piix: create PIIX4_PM device directly instead of using piix4_pm_initfn(), Philippe Mathieu-Daudé, 2022/06/11