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[PULL 09/49] target/mips: Fix emulation of nanoMIPS EXTRV_S.H instructio
From: |
Philippe Mathieu-Daudé |
Subject: |
[PULL 09/49] target/mips: Fix emulation of nanoMIPS EXTRV_S.H instruction |
Date: |
Sat, 11 Jun 2022 12:32:32 +0200 |
From: Dragan Mladjenovic <dragan.mladjenovic@syrmia.com>
The field rs in the instruction EXTRV_S.H rt, ac, rs is specified in
nanoMIPS documentation as opcode[20..16]. It is, however, erroneously
considered as opcode[25..21] in the current QEMU implementation. In
function gen_pool32axf_2_nanomips_insn(), the variable v0_t corresponds
to rt/opcode[25..21], and v1_t corresponds to rs/opcode[20..16]), and
v0_t is by mistake passed to the helper gen_helper_extr_s_h().
Use v1_t rather than v0_t in the invocation of gen_helper_extr_s_h()
to fix this.
Signed-off-by: Dragan Mladjenovic <dragan.mladjenovic@syrmia.com>
Signed-off-by: Stefan Pejic <stefan.pejic@syrmia.com>
Fixes: 8b3698b294 ("target/mips: Add emulation of DSP ASE for nanoMIPS")
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20220504110403.613168-3-stefan.pejic@syrmia.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/tcg/nanomips_translate.c.inc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/mips/tcg/nanomips_translate.c.inc
b/target/mips/tcg/nanomips_translate.c.inc
index 58ae35a156..9ee4df2135 100644
--- a/target/mips/tcg/nanomips_translate.c.inc
+++ b/target/mips/tcg/nanomips_translate.c.inc
@@ -2036,7 +2036,7 @@ static void gen_pool32axf_2_nanomips_insn(DisasContext
*ctx, uint32_t opc,
case NM_EXTRV_S_H:
check_dsp(ctx);
tcg_gen_movi_tl(t0, rd >> 3);
- gen_helper_extr_s_h(t0, t0, v0_t, cpu_env);
+ gen_helper_extr_s_h(t0, t0, v1_t, cpu_env);
gen_store_gpr(t0, ret);
break;
}
--
2.36.1
- [PULL 00/49] MIPS patches for 2022-06-11, Philippe Mathieu-Daudé, 2022/06/11
- [PULL 01/49] target/mips: Fix WatchHi.M handling, Philippe Mathieu-Daudé, 2022/06/11
- [PULL 02/49] target/mips: Fix SAT_S trans helper, Philippe Mathieu-Daudé, 2022/06/11
- [PULL 03/49] target/mips: Fix df_extract_val() and df_extract_df() dfe lookup, Philippe Mathieu-Daudé, 2022/06/11
- [PULL 04/49] target/mips: Fix msa checking condition in trans_msa_elm_fn(), Philippe Mathieu-Daudé, 2022/06/11
- [PULL 05/49] target/mips: Do not treat msa INSERT as NOP when wd is zero, Philippe Mathieu-Daudé, 2022/06/11
- [PULL 06/49] target/mips: Fix store adress of high 64bit in helper_msa_st_b(), Philippe Mathieu-Daudé, 2022/06/11
- [PULL 07/49] target/mips: Fix FTRUNC_S and FTRUNC_U trans helper, Philippe Mathieu-Daudé, 2022/06/11
- [PULL 08/49] target/mips: Fix emulation of nanoMIPS MTHLIP instruction, Philippe Mathieu-Daudé, 2022/06/11
- [PULL 09/49] target/mips: Fix emulation of nanoMIPS EXTRV_S.H instruction,
Philippe Mathieu-Daudé <=
- [PULL 10/49] target/mips: Fix emulation of nanoMIPS BPOSGE32C instruction, Philippe Mathieu-Daudé, 2022/06/11
- [PULL 11/49] target/mips: Fix emulation of nanoMIPS BNEC[32] instruction, Philippe Mathieu-Daudé, 2022/06/11
- [PULL 12/49] target/mips: Fix handling of unaligned memory access for nanoMIPS ISA, Philippe Mathieu-Daudé, 2022/06/11
- [PULL 13/49] target/mips: Add missing default cases for some nanoMIPS pools, Philippe Mathieu-Daudé, 2022/06/11
- [PULL 14/49] target/mips: Undeprecate nanoMIPS ISA support in QEMU, Philippe Mathieu-Daudé, 2022/06/11
- [PULL 15/49] hw/block/fdc-sysbus: Always mark sysbus floppy controllers as not having DMA, Philippe Mathieu-Daudé, 2022/06/11
- [PULL 16/49] hw/acpi/piix4: move xen_enabled() logic from piix4_pm_init() to piix4_pm_realize(), Philippe Mathieu-Daudé, 2022/06/11
- [PULL 17/49] hw/acpi/piix4: change smm_enabled from int to bool, Philippe Mathieu-Daudé, 2022/06/11
- [PULL 18/49] hw/acpi/piix4: convert smm_enabled bool to qdev property, Philippe Mathieu-Daudé, 2022/06/11
- [PULL 19/49] hw/acpi/piix4: move PIIX4PMState into separate piix4.h header, Philippe Mathieu-Daudé, 2022/06/11