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[PULL 20/49] hw/acpi/piix4: alter piix4_pm_init() to return PIIX4PMState
From: |
Philippe Mathieu-Daudé |
Subject: |
[PULL 20/49] hw/acpi/piix4: alter piix4_pm_init() to return PIIX4PMState |
Date: |
Sat, 11 Jun 2022 12:32:43 +0200 |
From: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
This exposes the PIIX4_PM device to the caller to allow any qdev gpios to be
mapped outside of piix4_pm_init().
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20220528091934.15520-6-mark.cave-ayland@ilande.co.uk>
Reviewed-by: Bernhard Beschow <shentey@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
hw/acpi/piix4.c | 11 ++++-------
hw/i386/pc_piix.c | 10 +++++-----
hw/isa/piix4.c | 8 +++++---
include/hw/southbridge/piix.h | 7 ++++---
4 files changed, 18 insertions(+), 18 deletions(-)
diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c
index c2177c5093..c4cfb75020 100644
--- a/hw/acpi/piix4.c
+++ b/hw/acpi/piix4.c
@@ -497,9 +497,9 @@ static void piix4_pm_realize(PCIDevice *dev, Error **errp)
piix4_pm_add_properties(s);
}
-I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
- qemu_irq sci_irq, qemu_irq smi_irq,
- bool smm_enabled, DeviceState **piix4_pm)
+PIIX4PMState *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
+ qemu_irq sci_irq, qemu_irq smi_irq,
+ bool smm_enabled)
{
PCIDevice *pci_dev;
DeviceState *dev;
@@ -509,9 +509,6 @@ I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t
smb_io_base,
dev = DEVICE(pci_dev);
qdev_prop_set_uint32(dev, "smb_io_base", smb_io_base);
qdev_prop_set_bit(dev, "smm-enabled", smm_enabled);
- if (piix4_pm) {
- *piix4_pm = dev;
- }
s = PIIX4_PM(dev);
s->irq = sci_irq;
@@ -519,7 +516,7 @@ I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t
smb_io_base,
pci_realize_and_unref(pci_dev, bus, &error_fatal);
- return s->smb.smbus;
+ return s;
}
static uint64_t gpe_readb(void *opaque, hwaddr addr, unsigned width)
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index bd63511c1c..3359b40f54 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -280,14 +280,14 @@ static void pc_init1(MachineState *machine,
}
if (pcmc->pci_enabled && x86_machine_is_acpi_enabled(X86_MACHINE(pcms))) {
- DeviceState *piix4_pm;
+ PIIX4PMState *piix4_pm;
smi_irq = qemu_allocate_irq(pc_acpi_smi_interrupt, first_cpu, 0);
+ piix4_pm = piix4_pm_init(pci_bus, piix3_devfn + 3, 0xb100,
+ x86ms->gsi[9], smi_irq,
+ x86_machine_is_smm_enabled(x86ms));
+ pcms->smbus = I2C_BUS(qdev_get_child_bus(DEVICE(piix4_pm), "i2c"));
/* TODO: Populate SPD eeprom data. */
- pcms->smbus = piix4_pm_init(pci_bus, piix3_devfn + 3, 0xb100,
- x86ms->gsi[9], smi_irq,
- x86_machine_is_smm_enabled(x86ms),
- &piix4_pm);
smbus_eeprom_init(pcms->smbus, 8, NULL, 0);
object_property_add_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP,
diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
index 8607e0ac36..7d9bedd1bb 100644
--- a/hw/isa/piix4.c
+++ b/hw/isa/piix4.c
@@ -293,6 +293,7 @@ static int pci_slot_get_pirq(PCIDevice *pci_dev, int
irq_num)
DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus, I2CBus **smbus)
{
PIIX4State *s;
+ PIIX4PMState *pms;
PCIDevice *pci;
DeviceState *dev;
int devfn = PCI_DEVFN(10, 0);
@@ -310,9 +311,10 @@ DeviceState *piix4_create(PCIBus *pci_bus, ISABus
**isa_bus, I2CBus **smbus)
pci_create_simple(pci_bus, devfn + 2, "piix4-usb-uhci");
if (smbus) {
- *smbus = piix4_pm_init(pci_bus, devfn + 3, 0x1100,
- qdev_get_gpio_in_named(dev, "isa", 9),
- NULL, 0, NULL);
+ pms = piix4_pm_init(pci_bus, devfn + 3, 0x1100,
+ qdev_get_gpio_in_named(dev, "isa", 9),
+ NULL, 0);
+ *smbus = I2C_BUS(qdev_get_child_bus(DEVICE(pms), "i2c"));
}
pci_bus_irqs(pci_bus, piix4_set_irq, pci_slot_get_pirq, s, PIIX_NUM_PIRQS);
diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h
index 04cbc3fe30..a362ec7484 100644
--- a/include/hw/southbridge/piix.h
+++ b/include/hw/southbridge/piix.h
@@ -14,10 +14,11 @@
#include "hw/pci/pci.h"
#include "qom/object.h"
+#include "hw/acpi/piix4.h"
-I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
- qemu_irq sci_irq, qemu_irq smi_irq,
- bool smm_enabled, DeviceState **piix4_pm);
+PIIX4PMState *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
+ qemu_irq sci_irq, qemu_irq smi_irq,
+ bool smm_enabled);
/* PIRQRC[A:D]: PIRQx Route Control Registers */
#define PIIX_PIRQCA 0x60
--
2.36.1
- [PULL 10/49] target/mips: Fix emulation of nanoMIPS BPOSGE32C instruction, (continued)
- [PULL 10/49] target/mips: Fix emulation of nanoMIPS BPOSGE32C instruction, Philippe Mathieu-Daudé, 2022/06/11
- [PULL 11/49] target/mips: Fix emulation of nanoMIPS BNEC[32] instruction, Philippe Mathieu-Daudé, 2022/06/11
- [PULL 12/49] target/mips: Fix handling of unaligned memory access for nanoMIPS ISA, Philippe Mathieu-Daudé, 2022/06/11
- [PULL 13/49] target/mips: Add missing default cases for some nanoMIPS pools, Philippe Mathieu-Daudé, 2022/06/11
- [PULL 14/49] target/mips: Undeprecate nanoMIPS ISA support in QEMU, Philippe Mathieu-Daudé, 2022/06/11
- [PULL 15/49] hw/block/fdc-sysbus: Always mark sysbus floppy controllers as not having DMA, Philippe Mathieu-Daudé, 2022/06/11
- [PULL 16/49] hw/acpi/piix4: move xen_enabled() logic from piix4_pm_init() to piix4_pm_realize(), Philippe Mathieu-Daudé, 2022/06/11
- [PULL 17/49] hw/acpi/piix4: change smm_enabled from int to bool, Philippe Mathieu-Daudé, 2022/06/11
- [PULL 18/49] hw/acpi/piix4: convert smm_enabled bool to qdev property, Philippe Mathieu-Daudé, 2022/06/11
- [PULL 19/49] hw/acpi/piix4: move PIIX4PMState into separate piix4.h header, Philippe Mathieu-Daudé, 2022/06/11
- [PULL 20/49] hw/acpi/piix4: alter piix4_pm_init() to return PIIX4PMState,
Philippe Mathieu-Daudé <=
- [PULL 21/49] hw/acpi/piix4: rename piix4_pm_init() to piix4_pm_initfn(), Philippe Mathieu-Daudé, 2022/06/11
- [PULL 22/49] hw/acpi/piix4: use qdev gpio to wire up sci_irq, Philippe Mathieu-Daudé, 2022/06/11
- [PULL 24/49] hw/i386/pc_piix: create PIIX4_PM device directly instead of using piix4_pm_initfn(), Philippe Mathieu-Daudé, 2022/06/11
- [PULL 23/49] hw/acpi/piix4: use qdev gpio to wire up smi_irq, Philippe Mathieu-Daudé, 2022/06/11
- [PULL 25/49] hw/isa/piix4.c: create PIIX4_PM device directly instead of using piix4_pm_initfn(), Philippe Mathieu-Daudé, 2022/06/11
- [PULL 26/49] hw/acpi/piix4: remove unused piix4_pm_initfn() function, Philippe Mathieu-Daudé, 2022/06/11
- [PULL 27/49] hw/southbridge/piix: Aggregate all PIIX southbridge type names, Philippe Mathieu-Daudé, 2022/06/11
- [PULL 28/49] hw/isa/piix4: Use object_initialize_child() for embedded struct, Philippe Mathieu-Daudé, 2022/06/11
- [PULL 29/49] hw/isa/piix4: Move pci_map_irq_fn' near pci_set_irq_fn, Philippe Mathieu-Daudé, 2022/06/11
- [PULL 30/49] hw/isa/piix4: QOM'ify PCI device creation and wiring, Philippe Mathieu-Daudé, 2022/06/11