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[PULL 06/61] target/riscv: Implement function kvm_arch_init_vcpu
From: |
Alistair Francis |
Subject: |
[PULL 06/61] target/riscv: Implement function kvm_arch_init_vcpu |
Date: |
Fri, 21 Jan 2022 15:57:35 +1000 |
From: Yifei Jiang <jiangyifei@huawei.com>
Get isa info from kvm while kvm init.
Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Mingwang Li <limingwang@huawei.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Message-id: 20220112081329.1835-4-jiangyifei@huawei.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/kvm.c | 34 +++++++++++++++++++++++++++++++++-
1 file changed, 33 insertions(+), 1 deletion(-)
diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
index 687dd4b621..9e66b4a97f 100644
--- a/target/riscv/kvm.c
+++ b/target/riscv/kvm.c
@@ -38,6 +38,24 @@
#include "qemu/log.h"
#include "hw/loader.h"
+static uint64_t kvm_riscv_reg_id(CPURISCVState *env, uint64_t type,
+ uint64_t idx)
+{
+ uint64_t id = KVM_REG_RISCV | type | idx;
+
+ switch (riscv_cpu_mxl(env)) {
+ case MXL_RV32:
+ id |= KVM_REG_SIZE_U32;
+ break;
+ case MXL_RV64:
+ id |= KVM_REG_SIZE_U64;
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ return id;
+}
+
const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
KVM_CAP_LAST_INFO
};
@@ -79,7 +97,21 @@ void kvm_arch_init_irq_routing(KVMState *s)
int kvm_arch_init_vcpu(CPUState *cs)
{
- return 0;
+ int ret = 0;
+ target_ulong isa;
+ RISCVCPU *cpu = RISCV_CPU(cs);
+ CPURISCVState *env = &cpu->env;
+ uint64_t id;
+
+ id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG,
+ KVM_REG_RISCV_CONFIG_REG(isa));
+ ret = kvm_get_one_reg(cs, id, &isa);
+ if (ret) {
+ return ret;
+ }
+ env->misa_ext = isa;
+
+ return ret;
}
int kvm_arch_msi_data_to_gsi(uint32_t data)
--
2.31.1
- [PULL 00/61] riscv-to-apply queue, Alistair Francis, 2022/01/21
- [PULL 01/61] hw: timer: ibex_timer: Fixup reading w/o register, Alistair Francis, 2022/01/21
- [PULL 02/61] riscv: opentitan: fixup plic stride len, Alistair Francis, 2022/01/21
- [PULL 03/61] hw: timer: ibex_timer: update/add reg address, Alistair Francis, 2022/01/21
- [PULL 04/61] update-linux-headers: Add asm-riscv/kvm.h, Alistair Francis, 2022/01/21
- [PULL 05/61] target/riscv: Add target/riscv/kvm.c to place the public kvm interface, Alistair Francis, 2022/01/21
- [PULL 07/61] target/riscv: Implement kvm_arch_get_registers, Alistair Francis, 2022/01/21
- [PULL 10/61] target/riscv: Support setting external interrupt by KVM, Alistair Francis, 2022/01/21
- [PULL 20/61] target/riscv: rvv-1.0: Add Zve64f support for configuration insns, Alistair Francis, 2022/01/21
- [PULL 06/61] target/riscv: Implement function kvm_arch_init_vcpu,
Alistair Francis <=
- [PULL 09/61] target/riscv: Support start kernel directly by KVM, Alistair Francis, 2022/01/21
- [PULL 11/61] target/riscv: Handle KVM_EXIT_RISCV_SBI exit, Alistair Francis, 2022/01/21
- [PULL 12/61] target/riscv: Add host cpu type, Alistair Francis, 2022/01/21
- [PULL 13/61] target/riscv: Add kvm_riscv_get/put_regs_timer, Alistair Francis, 2022/01/21
- [PULL 08/61] target/riscv: Implement kvm_arch_put_registers, Alistair Francis, 2022/01/21
- [PULL 14/61] target/riscv: Implement virtual time adjusting with vm state changing, Alistair Francis, 2022/01/21
- [PULL 15/61] target/riscv: Support virtual time context synchronization, Alistair Francis, 2022/01/21
- [PULL 16/61] target/riscv: enable riscv kvm accel, Alistair Francis, 2022/01/21
- [PULL 17/61] softmmu/device_tree: Silence compiler warning with --enable-sanitizers, Alistair Francis, 2022/01/21
- [PULL 18/61] softmmu/device_tree: Remove redundant pointer assignment, Alistair Francis, 2022/01/21