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[PULL 01/61] hw: timer: ibex_timer: Fixup reading w/o register
From: |
Alistair Francis |
Subject: |
[PULL 01/61] hw: timer: ibex_timer: Fixup reading w/o register |
Date: |
Fri, 21 Jan 2022 15:57:30 +1000 |
From: Wilfred Mallawa <wilfred.mallawa@wdc.com>
This change fixes a bug where a write only register is read.
As per https://docs.opentitan.org/hw/ip/rv_timer/doc/#register-table
the 'INTR_TEST0' register is write only.
Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20220110051606.4031241-1-alistair.francis@opensource.wdc.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
include/hw/timer/ibex_timer.h | 1 -
hw/timer/ibex_timer.c | 14 +++++---------
2 files changed, 5 insertions(+), 10 deletions(-)
diff --git a/include/hw/timer/ibex_timer.h b/include/hw/timer/ibex_timer.h
index b6f69b38ee..1a0a28d5fa 100644
--- a/include/hw/timer/ibex_timer.h
+++ b/include/hw/timer/ibex_timer.h
@@ -43,7 +43,6 @@ struct IbexTimerState {
uint32_t timer_compare_upper0;
uint32_t timer_intr_enable;
uint32_t timer_intr_state;
- uint32_t timer_intr_test;
uint32_t timebase_freq;
diff --git a/hw/timer/ibex_timer.c b/hw/timer/ibex_timer.c
index 66e1f8e48c..826c38b653 100644
--- a/hw/timer/ibex_timer.c
+++ b/hw/timer/ibex_timer.c
@@ -130,7 +130,6 @@ static void ibex_timer_reset(DeviceState *dev)
s->timer_compare_upper0 = 0xFFFFFFFF;
s->timer_intr_enable = 0x00000000;
s->timer_intr_state = 0x00000000;
- s->timer_intr_test = 0x00000000;
ibex_timer_update_irqs(s);
}
@@ -168,7 +167,8 @@ static uint64_t ibex_timer_read(void *opaque, hwaddr addr,
retvalue = s->timer_intr_state;
break;
case R_INTR_TEST:
- retvalue = s->timer_intr_test;
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "Attempted to read INTR_TEST, a write only register");
break;
default:
qemu_log_mask(LOG_GUEST_ERROR,
@@ -215,10 +215,7 @@ static void ibex_timer_write(void *opaque, hwaddr addr,
s->timer_intr_state &= ~val;
break;
case R_INTR_TEST:
- s->timer_intr_test = val;
- if (s->timer_intr_enable &
- s->timer_intr_test &
- R_INTR_ENABLE_IE_0_MASK) {
+ if (s->timer_intr_enable & val & R_INTR_ENABLE_IE_0_MASK) {
s->timer_intr_state |= R_INTR_STATE_IS_0_MASK;
qemu_set_irq(s->irq, true);
}
@@ -247,8 +244,8 @@ static int ibex_timer_post_load(void *opaque, int
version_id)
static const VMStateDescription vmstate_ibex_timer = {
.name = TYPE_IBEX_TIMER,
- .version_id = 1,
- .minimum_version_id = 1,
+ .version_id = 2,
+ .minimum_version_id = 2,
.post_load = ibex_timer_post_load,
.fields = (VMStateField[]) {
VMSTATE_UINT32(timer_ctrl, IbexTimerState),
@@ -257,7 +254,6 @@ static const VMStateDescription vmstate_ibex_timer = {
VMSTATE_UINT32(timer_compare_upper0, IbexTimerState),
VMSTATE_UINT32(timer_intr_enable, IbexTimerState),
VMSTATE_UINT32(timer_intr_state, IbexTimerState),
- VMSTATE_UINT32(timer_intr_test, IbexTimerState),
VMSTATE_END_OF_LIST()
}
};
--
2.31.1
- [PULL 00/61] riscv-to-apply queue, Alistair Francis, 2022/01/21
- [PULL 01/61] hw: timer: ibex_timer: Fixup reading w/o register,
Alistair Francis <=
- [PULL 02/61] riscv: opentitan: fixup plic stride len, Alistair Francis, 2022/01/21
- [PULL 03/61] hw: timer: ibex_timer: update/add reg address, Alistair Francis, 2022/01/21
- [PULL 04/61] update-linux-headers: Add asm-riscv/kvm.h, Alistair Francis, 2022/01/21
- [PULL 05/61] target/riscv: Add target/riscv/kvm.c to place the public kvm interface, Alistair Francis, 2022/01/21
- [PULL 07/61] target/riscv: Implement kvm_arch_get_registers, Alistair Francis, 2022/01/21
- [PULL 10/61] target/riscv: Support setting external interrupt by KVM, Alistair Francis, 2022/01/21
- [PULL 20/61] target/riscv: rvv-1.0: Add Zve64f support for configuration insns, Alistair Francis, 2022/01/21
- [PULL 06/61] target/riscv: Implement function kvm_arch_init_vcpu, Alistair Francis, 2022/01/21
- [PULL 09/61] target/riscv: Support start kernel directly by KVM, Alistair Francis, 2022/01/21
- [PULL 11/61] target/riscv: Handle KVM_EXIT_RISCV_SBI exit, Alistair Francis, 2022/01/21