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[PULL 10/61] target/riscv: Support setting external interrupt by KVM
From: |
Alistair Francis |
Subject: |
[PULL 10/61] target/riscv: Support setting external interrupt by KVM |
Date: |
Fri, 21 Jan 2022 15:57:39 +1000 |
From: Yifei Jiang <jiangyifei@huawei.com>
When KVM is enabled, set the S-mode external interrupt through
kvm_riscv_set_irq function.
Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Mingwang Li <limingwang@huawei.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Message-id: 20220112081329.1835-8-jiangyifei@huawei.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/kvm_riscv.h | 1 +
target/riscv/cpu.c | 6 +++++-
target/riscv/kvm-stub.c | 5 +++++
target/riscv/kvm.c | 17 +++++++++++++++++
4 files changed, 28 insertions(+), 1 deletion(-)
diff --git a/target/riscv/kvm_riscv.h b/target/riscv/kvm_riscv.h
index f38c82bf59..ed281bdce0 100644
--- a/target/riscv/kvm_riscv.h
+++ b/target/riscv/kvm_riscv.h
@@ -20,5 +20,6 @@
#define QEMU_KVM_RISCV_H
void kvm_riscv_reset_vcpu(RISCVCPU *cpu);
+void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level);
#endif
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index a6922dde05..53b0524830 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -630,7 +630,11 @@ static void riscv_cpu_set_irq(void *opaque, int irq, int
level)
case IRQ_S_EXT:
case IRQ_VS_EXT:
case IRQ_M_EXT:
- riscv_cpu_update_mip(cpu, 1 << irq, BOOL_TO_MASK(level));
+ if (kvm_enabled()) {
+ kvm_riscv_set_irq(cpu, irq, level);
+ } else {
+ riscv_cpu_update_mip(cpu, 1 << irq, BOOL_TO_MASK(level));
+ }
break;
default:
g_assert_not_reached();
diff --git a/target/riscv/kvm-stub.c b/target/riscv/kvm-stub.c
index 39b96fe3f4..4e8fc31a21 100644
--- a/target/riscv/kvm-stub.c
+++ b/target/riscv/kvm-stub.c
@@ -23,3 +23,8 @@ void kvm_riscv_reset_vcpu(RISCVCPU *cpu)
{
abort();
}
+
+void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level)
+{
+ abort();
+}
diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
index d5c6a9d41a..0ba64795d5 100644
--- a/target/riscv/kvm.c
+++ b/target/riscv/kvm.c
@@ -385,6 +385,23 @@ void kvm_riscv_reset_vcpu(RISCVCPU *cpu)
env->satp = 0;
}
+void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level)
+{
+ int ret;
+ unsigned virq = level ? KVM_INTERRUPT_SET : KVM_INTERRUPT_UNSET;
+
+ if (irq != IRQ_S_EXT) {
+ perror("kvm riscv set irq != IRQ_S_EXT\n");
+ abort();
+ }
+
+ ret = kvm_vcpu_ioctl(CPU(cpu), KVM_INTERRUPT, &virq);
+ if (ret < 0) {
+ perror("Set irq failed");
+ abort();
+ }
+}
+
bool kvm_arch_cpu_check_are_resettable(void)
{
return true;
--
2.31.1
- [PULL 00/61] riscv-to-apply queue, Alistair Francis, 2022/01/21
- [PULL 01/61] hw: timer: ibex_timer: Fixup reading w/o register, Alistair Francis, 2022/01/21
- [PULL 02/61] riscv: opentitan: fixup plic stride len, Alistair Francis, 2022/01/21
- [PULL 03/61] hw: timer: ibex_timer: update/add reg address, Alistair Francis, 2022/01/21
- [PULL 04/61] update-linux-headers: Add asm-riscv/kvm.h, Alistair Francis, 2022/01/21
- [PULL 05/61] target/riscv: Add target/riscv/kvm.c to place the public kvm interface, Alistair Francis, 2022/01/21
- [PULL 07/61] target/riscv: Implement kvm_arch_get_registers, Alistair Francis, 2022/01/21
- [PULL 10/61] target/riscv: Support setting external interrupt by KVM,
Alistair Francis <=
- [PULL 20/61] target/riscv: rvv-1.0: Add Zve64f support for configuration insns, Alistair Francis, 2022/01/21
- [PULL 06/61] target/riscv: Implement function kvm_arch_init_vcpu, Alistair Francis, 2022/01/21
- [PULL 09/61] target/riscv: Support start kernel directly by KVM, Alistair Francis, 2022/01/21
- [PULL 11/61] target/riscv: Handle KVM_EXIT_RISCV_SBI exit, Alistair Francis, 2022/01/21
- [PULL 12/61] target/riscv: Add host cpu type, Alistair Francis, 2022/01/21
- [PULL 13/61] target/riscv: Add kvm_riscv_get/put_regs_timer, Alistair Francis, 2022/01/21
- [PULL 08/61] target/riscv: Implement kvm_arch_put_registers, Alistair Francis, 2022/01/21
- [PULL 14/61] target/riscv: Implement virtual time adjusting with vm state changing, Alistair Francis, 2022/01/21
- [PULL 15/61] target/riscv: Support virtual time context synchronization, Alistair Francis, 2022/01/21
- [PULL 16/61] target/riscv: enable riscv kvm accel, Alistair Francis, 2022/01/21