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[PULL 62/88] target/riscv: rvv-1.0: widening floating-point reduction in
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From: |
Alistair Francis |
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Subject: |
[PULL 62/88] target/riscv: rvv-1.0: widening floating-point reduction instructions |
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Date: |
Mon, 20 Dec 2021 14:56:39 +1000 |
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211210075704.23951-55-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/insn_trans/trans_rvv.c.inc | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index 998247d71d..b43234ed3f 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -2648,7 +2648,14 @@ GEN_OPFVV_TRANS(vfredmax_vs, freduction_check)
GEN_OPFVV_TRANS(vfredmin_vs, freduction_check)
/* Vector Widening Floating-Point Reduction Instructions */
-GEN_OPFVV_WIDEN_TRANS(vfwredsum_vs, reduction_check)
+static bool freduction_widen_check(DisasContext *s, arg_rmrr *a)
+{
+ return reduction_widen_check(s, a) &&
+ require_scale_rvf(s) &&
+ (s->sew != MO_8);
+}
+
+GEN_OPFVV_WIDEN_TRANS(vfwredsum_vs, freduction_widen_check)
/*
*** Vector Mask Operations
--
2.31.1
- [PULL 65/88] target/riscv: rvv-1.0: remove vmford.vv and vmford.vf, (continued)
- [PULL 65/88] target/riscv: rvv-1.0: remove vmford.vv and vmford.vf, Alistair Francis, 2021/12/20
- [PULL 86/88] riscv: Set 5.4 as minimum kernel version for riscv32, Alistair Francis, 2021/12/20
- [PULL 73/88] target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits, Alistair Francis, 2021/12/20
- [PULL 77/88] target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruction, Alistair Francis, 2021/12/20
- [PULL 63/88] target/riscv: rvv-1.0: single-width scaling shift instructions, Alistair Francis, 2021/12/20
- [PULL 74/88] target/riscv: rvv-1.0: implement vstart CSR, Alistair Francis, 2021/12/20
- [PULL 58/88] target/riscv: rvv-1.0: slide instructions, Alistair Francis, 2021/12/20
- [PULL 64/88] target/riscv: rvv-1.0: remove widening saturating scaled multiply-add, Alistair Francis, 2021/12/20
- [PULL 71/88] target/riscv: add "set round to odd" rounding mode helper function, Alistair Francis, 2021/12/20
- [PULL 66/88] target/riscv: rvv-1.0: remove integer extract instruction, Alistair Francis, 2021/12/20
- [PULL 62/88] target/riscv: rvv-1.0: widening floating-point reduction instructions,
Alistair Francis <=
- [PULL 88/88] hw/riscv: Use load address rather than entry point for fw_dynamic next_addr, Alistair Francis, 2021/12/20
- [PULL 82/88] target/riscv: rvv-1.0: add vector unit-stride mask load/store insns, Alistair Francis, 2021/12/20
- [PULL 69/88] target/riscv: rvv-1.0: floating-point/integer type-convert instructions, Alistair Francis, 2021/12/20
- [PULL 72/88] target/riscv: rvv-1.0: narrowing floating-point/integer type-convert, Alistair Francis, 2021/12/20
- [PULL 59/88] target/riscv: rvv-1.0: floating-point slide instructions, Alistair Francis, 2021/12/20
- [PULL 76/88] target/riscv: gdb: support vector registers for rv64 & rv32, Alistair Francis, 2021/12/20
- [PULL 79/88] target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11, Alistair Francis, 2021/12/20
- [PULL 80/88] target/riscv: rvv-1.0: add vsetivli instruction, Alistair Francis, 2021/12/20
- [PULL 68/88] target/riscv: introduce floating-point rounding mode enum, Alistair Francis, 2021/12/20
- [PULL 81/88] target/riscv: rvv-1.0: add evl parameter to vext_ldst_us(), Alistair Francis, 2021/12/20