[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL 73/88] target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits
From: |
Alistair Francis |
Subject: |
[PULL 73/88] target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits |
Date: |
Mon, 20 Dec 2021 14:56:50 +1000 |
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-66-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 2 +-
target/riscv/vector_helper.c | 2 +-
target/riscv/insn_trans/trans_rvv.c.inc | 4 ++--
3 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 11a0f41b27..5d93ccdfa7 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -100,7 +100,7 @@ typedef struct CPURISCVState CPURISCVState;
#include "pmp.h"
#endif
-#define RV_VLEN_MAX 256
+#define RV_VLEN_MAX 1024
FIELD(VTYPE, VLMUL, 0, 3)
FIELD(VTYPE, VSEW, 3, 3)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index a78f36b4b3..e61c873142 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -124,7 +124,7 @@ static inline int32_t vext_lmul(uint32_t desc)
static inline uint32_t vext_max_elems(uint32_t desc, uint32_t esz)
{
/*
- * As simd_desc support at most 256 bytes, the max vlen is 256 bits.
+ * As simd_desc support at most 2048 bytes, the max vlen is 1024 bits.
* so vlen in bytes (vlenb) is encoded as maxsz.
*/
uint32_t vlenb = simd_maxsz(desc);
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index 42e9449118..be3f9f1327 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -567,8 +567,8 @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1,
uint32_t data,
base = get_gpr(s, rs1, EXT_NONE);
/*
- * As simd_desc supports at most 256 bytes, and in this implementation,
- * the max vector group length is 2048 bytes. So split it into two parts.
+ * As simd_desc supports at most 2048 bytes, and in this implementation,
+ * the max vector group length is 4096 bytes. So split it into two parts.
*
* The first part is vlen in bytes, encoded in maxsz of simd_desc.
* The second part is lmul, encoded in data of simd_desc.
--
2.31.1
- [PULL 60/88] target/riscv: rvv-1.0: narrowing fixed-point clip instructions, (continued)
- [PULL 60/88] target/riscv: rvv-1.0: narrowing fixed-point clip instructions, Alistair Francis, 2021/12/20
- [PULL 67/88] target/riscv: rvv-1.0: floating-point min/max instructions, Alistair Francis, 2021/12/20
- [PULL 87/88] target/riscv: Enable bitmanip Zb[abcs] instructions, Alistair Francis, 2021/12/20
- [PULL 84/88] target/riscv: rvv-1.0: update opivv_vadc_check() comment, Alistair Francis, 2021/12/20
- [PULL 43/88] target/riscv: rvv-1.0: register gather instructions, Alistair Francis, 2021/12/20
- [PULL 48/88] target/riscv: rvv-1.0: integer extension instructions, Alistair Francis, 2021/12/20
- [PULL 55/88] target/riscv: rvv-1.0: integer comparison instructions, Alistair Francis, 2021/12/20
- [PULL 61/88] target/riscv: rvv-1.0: single-width floating-point reduction, Alistair Francis, 2021/12/20
- [PULL 65/88] target/riscv: rvv-1.0: remove vmford.vv and vmford.vf, Alistair Francis, 2021/12/20
- [PULL 86/88] riscv: Set 5.4 as minimum kernel version for riscv32, Alistair Francis, 2021/12/20
- [PULL 73/88] target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits,
Alistair Francis <=
- [PULL 77/88] target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruction, Alistair Francis, 2021/12/20
- [PULL 63/88] target/riscv: rvv-1.0: single-width scaling shift instructions, Alistair Francis, 2021/12/20
- [PULL 74/88] target/riscv: rvv-1.0: implement vstart CSR, Alistair Francis, 2021/12/20
- [PULL 58/88] target/riscv: rvv-1.0: slide instructions, Alistair Francis, 2021/12/20
- [PULL 64/88] target/riscv: rvv-1.0: remove widening saturating scaled multiply-add, Alistair Francis, 2021/12/20
- [PULL 71/88] target/riscv: add "set round to odd" rounding mode helper function, Alistair Francis, 2021/12/20
- [PULL 66/88] target/riscv: rvv-1.0: remove integer extract instruction, Alistair Francis, 2021/12/20
- [PULL 62/88] target/riscv: rvv-1.0: widening floating-point reduction instructions, Alistair Francis, 2021/12/20
- [PULL 88/88] hw/riscv: Use load address rather than entry point for fw_dynamic next_addr, Alistair Francis, 2021/12/20
- [PULL 82/88] target/riscv: rvv-1.0: add vector unit-stride mask load/store insns, Alistair Francis, 2021/12/20