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[PULL 68/88] target/riscv: introduce floating-point rounding mode enum
From: |
Alistair Francis |
Subject: |
[PULL 68/88] target/riscv: introduce floating-point rounding mode enum |
Date: |
Mon, 20 Dec 2021 14:56:45 +1000 |
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211210075704.23951-61-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/internals.h | 9 +++++++++
target/riscv/fpu_helper.c | 12 ++++++------
target/riscv/insn_trans/trans_rvv.c.inc | 18 +++++++++---------
3 files changed, 24 insertions(+), 15 deletions(-)
diff --git a/target/riscv/internals.h b/target/riscv/internals.h
index ac062dc0b4..db105d4d64 100644
--- a/target/riscv/internals.h
+++ b/target/riscv/internals.h
@@ -36,6 +36,15 @@ target_ulong fclass_d(uint64_t frs1);
extern const VMStateDescription vmstate_riscv_cpu;
#endif
+enum {
+ RISCV_FRM_RNE = 0, /* Round to Nearest, ties to Even */
+ RISCV_FRM_RTZ = 1, /* Round towards Zero */
+ RISCV_FRM_RDN = 2, /* Round Down */
+ RISCV_FRM_RUP = 3, /* Round Up */
+ RISCV_FRM_RMM = 4, /* Round to Nearest, ties to Max Magnitude */
+ RISCV_FRM_DYN = 7, /* Dynamic rounding mode */
+};
+
static inline uint64_t nanbox_s(float32 f)
{
return f | MAKE_64BIT_MASK(32, 32);
diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c
index 388e23ca67..dec39d4a9e 100644
--- a/target/riscv/fpu_helper.c
+++ b/target/riscv/fpu_helper.c
@@ -55,23 +55,23 @@ void helper_set_rounding_mode(CPURISCVState *env, uint32_t
rm)
{
int softrm;
- if (rm == 7) {
+ if (rm == RISCV_FRM_DYN) {
rm = env->frm;
}
switch (rm) {
- case 0:
+ case RISCV_FRM_RNE:
softrm = float_round_nearest_even;
break;
- case 1:
+ case RISCV_FRM_RTZ:
softrm = float_round_to_zero;
break;
- case 2:
+ case RISCV_FRM_RDN:
softrm = float_round_down;
break;
- case 3:
+ case RISCV_FRM_RUP:
softrm = float_round_up;
break;
- case 4:
+ case RISCV_FRM_RMM:
softrm = float_round_ties_away;
break;
default:
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index 1ce5a10b6a..047be5d5c4 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -2088,7 +2088,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)
\
gen_helper_##NAME##_d, \
}; \
TCGLabel *over = gen_new_label(); \
- gen_set_rm(s, 7); \
+ gen_set_rm(s, RISCV_FRM_DYN); \
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
@@ -2167,7 +2167,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)
\
gen_helper_##NAME##_w, \
gen_helper_##NAME##_d, \
}; \
- gen_set_rm(s, 7); \
+ gen_set_rm(s, RISCV_FRM_DYN); \
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
return opfvf_trans(a->rd, a->rs1, a->rs2, data, \
@@ -2199,7 +2199,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)
\
gen_helper_##NAME##_h, gen_helper_##NAME##_w, \
}; \
TCGLabel *over = gen_new_label(); \
- gen_set_rm(s, 7); \
+ gen_set_rm(s, RISCV_FRM_DYN); \
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
@@ -2236,7 +2236,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)
\
static gen_helper_opfvf *const fns[2] = { \
gen_helper_##NAME##_h, gen_helper_##NAME##_w, \
}; \
- gen_set_rm(s, 7); \
+ gen_set_rm(s, RISCV_FRM_DYN); \
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
return opfvf_trans(a->rd, a->rs1, a->rs2, data, \
@@ -2266,7 +2266,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)
\
gen_helper_##NAME##_h, gen_helper_##NAME##_w, \
}; \
TCGLabel *over = gen_new_label(); \
- gen_set_rm(s, 7); \
+ gen_set_rm(s, RISCV_FRM_DYN); \
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
@@ -2303,7 +2303,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)
\
static gen_helper_opfvf *const fns[2] = { \
gen_helper_##NAME##_h, gen_helper_##NAME##_w, \
}; \
- gen_set_rm(s, 7); \
+ gen_set_rm(s, RISCV_FRM_DYN); \
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
return opfvf_trans(a->rd, a->rs1, a->rs2, data, \
@@ -2380,7 +2380,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)
\
gen_helper_##NAME##_d, \
}; \
TCGLabel *over = gen_new_label(); \
- gen_set_rm(s, 7); \
+ gen_set_rm(s, RISCV_FRM_DYN); \
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
@@ -2526,7 +2526,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)
\
gen_helper_##NAME##_w, \
}; \
TCGLabel *over = gen_new_label(); \
- gen_set_rm(s, 7); \
+ gen_set_rm(s, RISCV_FRM_DYN); \
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
@@ -2574,7 +2574,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)
\
gen_helper_##NAME##_w, \
}; \
TCGLabel *over = gen_new_label(); \
- gen_set_rm(s, 7); \
+ gen_set_rm(s, RISCV_FRM_DYN); \
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
--
2.31.1
- [PULL 66/88] target/riscv: rvv-1.0: remove integer extract instruction, (continued)
- [PULL 66/88] target/riscv: rvv-1.0: remove integer extract instruction, Alistair Francis, 2021/12/20
- [PULL 62/88] target/riscv: rvv-1.0: widening floating-point reduction instructions, Alistair Francis, 2021/12/20
- [PULL 88/88] hw/riscv: Use load address rather than entry point for fw_dynamic next_addr, Alistair Francis, 2021/12/20
- [PULL 82/88] target/riscv: rvv-1.0: add vector unit-stride mask load/store insns, Alistair Francis, 2021/12/20
- [PULL 69/88] target/riscv: rvv-1.0: floating-point/integer type-convert instructions, Alistair Francis, 2021/12/20
- [PULL 72/88] target/riscv: rvv-1.0: narrowing floating-point/integer type-convert, Alistair Francis, 2021/12/20
- [PULL 59/88] target/riscv: rvv-1.0: floating-point slide instructions, Alistair Francis, 2021/12/20
- [PULL 76/88] target/riscv: gdb: support vector registers for rv64 & rv32, Alistair Francis, 2021/12/20
- [PULL 79/88] target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11, Alistair Francis, 2021/12/20
- [PULL 80/88] target/riscv: rvv-1.0: add vsetivli instruction, Alistair Francis, 2021/12/20
- [PULL 68/88] target/riscv: introduce floating-point rounding mode enum,
Alistair Francis <=
- [PULL 81/88] target/riscv: rvv-1.0: add evl parameter to vext_ldst_us(), Alistair Francis, 2021/12/20
- [PULL 70/88] target/riscv: rvv-1.0: widening floating-point/integer type-convert, Alistair Francis, 2021/12/20
- [PULL 83/88] target/riscv: rvv-1.0: rename vmandnot.mm and vmornot.mm to vmandn.mm and vmorn.mm, Alistair Francis, 2021/12/20
- Re: [PULL 00/88] riscv-to-apply queue, Richard Henderson, 2021/12/20