[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL 06/88] target/riscv: zfh: add Zfh cpu property
|
From: |
Alistair Francis |
|
Subject: |
[PULL 06/88] target/riscv: zfh: add Zfh cpu property |
|
Date: |
Mon, 20 Dec 2021 14:55:43 +1000 |
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20211210074329.5775-7-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index f812998123..0f808a5bee 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -629,6 +629,7 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
+ DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false),
DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
--
2.31.1
- [PULL 00/88] riscv-to-apply queue, Alistair Francis, 2021/12/19
- [PULL 01/88] target/riscv: zfh: half-precision load and store, Alistair Francis, 2021/12/19
- [PULL 02/88] target/riscv: zfh: half-precision computational, Alistair Francis, 2021/12/19
- [PULL 03/88] target/riscv: zfh: half-precision convert and move, Alistair Francis, 2021/12/19
- [PULL 04/88] target/riscv: zfh: half-precision floating-point compare, Alistair Francis, 2021/12/19
- [PULL 05/88] target/riscv: zfh: half-precision floating-point classify, Alistair Francis, 2021/12/19
- [PULL 06/88] target/riscv: zfh: add Zfh cpu property,
Alistair Francis <=
- [PULL 07/88] target/riscv: zfh: implement zfhmin extension, Alistair Francis, 2021/12/19
- [PULL 09/88] target/riscv: drop vector 0.7.1 and add 1.0 support, Alistair Francis, 2021/12/19
- [PULL 08/88] target/riscv: zfh: add Zfhmin cpu property, Alistair Francis, 2021/12/19
- [PULL 11/88] target/riscv: rvv-1.0: add mstatus VS field, Alistair Francis, 2021/12/19
- [PULL 12/88] target/riscv: rvv-1.0: set mstatus.SD bit if mstatus.VS is dirty, Alistair Francis, 2021/12/19
- [PULL 10/88] target/riscv: Use FIELD_EX32() to extract wd field, Alistair Francis, 2021/12/19
- [PULL 13/88] target/riscv: rvv-1.0: add sstatus VS field, Alistair Francis, 2021/12/19
- [PULL 14/88] target/riscv: rvv-1.0: introduce writable misa.v field, Alistair Francis, 2021/12/19
- [PULL 15/88] target/riscv: rvv-1.0: add translation-time vector context status, Alistair Francis, 2021/12/19
- [PULL 17/88] target/riscv: rvv-1.0: add vcsr register, Alistair Francis, 2021/12/19