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[PULL 17/88] target/riscv: rvv-1.0: add vcsr register
From: |
Alistair Francis |
Subject: |
[PULL 17/88] target/riscv: rvv-1.0: add vcsr register |
Date: |
Mon, 20 Dec 2021 14:55:54 +1000 |
From: LIU Zhiwei <zhiwei_liu@c-sky.com>
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-10-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_bits.h | 7 +++++++
target/riscv/csr.c | 17 +++++++++++++++++
2 files changed, 24 insertions(+)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index bb62da7549..8dc6aa62c6 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -60,9 +60,16 @@
#define CSR_VSTART 0x008
#define CSR_VXSAT 0x009
#define CSR_VXRM 0x00a
+#define CSR_VCSR 0x00f
#define CSR_VL 0xc20
#define CSR_VTYPE 0xc21
+/* VCSR fields */
+#define VCSR_VXSAT_SHIFT 0
+#define VCSR_VXSAT (0x1 << VCSR_VXSAT_SHIFT)
+#define VCSR_VXRM_SHIFT 1
+#define VCSR_VXRM (0x3 << VCSR_VXRM_SHIFT)
+
/* User Timers and Counters */
#define CSR_CYCLE 0xc00
#define CSR_TIME 0xc01
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index c522260986..832ccdcf33 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -336,6 +336,22 @@ static RISCVException write_vstart(CPURISCVState *env, int
csrno,
return RISCV_EXCP_NONE;
}
+static int read_vcsr(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ *val = (env->vxrm << VCSR_VXRM_SHIFT) | (env->vxsat << VCSR_VXSAT_SHIFT);
+ return RISCV_EXCP_NONE;
+}
+
+static int write_vcsr(CPURISCVState *env, int csrno, target_ulong val)
+{
+#if !defined(CONFIG_USER_ONLY)
+ env->mstatus |= MSTATUS_VS;
+#endif
+ env->vxrm = (val & VCSR_VXRM) >> VCSR_VXRM_SHIFT;
+ env->vxsat = (val & VCSR_VXSAT) >> VCSR_VXSAT_SHIFT;
+ return RISCV_EXCP_NONE;
+}
+
/* User Timers and Counters */
static RISCVException read_instret(CPURISCVState *env, int csrno,
target_ulong *val)
@@ -1816,6 +1832,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_VSTART] = { "vstart", vs, read_vstart, write_vstart },
[CSR_VXSAT] = { "vxsat", vs, read_vxsat, write_vxsat },
[CSR_VXRM] = { "vxrm", vs, read_vxrm, write_vxrm },
+ [CSR_VCSR] = { "vcsr", vs, read_vcsr, write_vcsr },
[CSR_VL] = { "vl", vs, read_vl },
[CSR_VTYPE] = { "vtype", vs, read_vtype },
/* User Timers and Counters */
--
2.31.1
- [PULL 06/88] target/riscv: zfh: add Zfh cpu property, (continued)
- [PULL 06/88] target/riscv: zfh: add Zfh cpu property, Alistair Francis, 2021/12/19
- [PULL 07/88] target/riscv: zfh: implement zfhmin extension, Alistair Francis, 2021/12/19
- [PULL 09/88] target/riscv: drop vector 0.7.1 and add 1.0 support, Alistair Francis, 2021/12/19
- [PULL 08/88] target/riscv: zfh: add Zfhmin cpu property, Alistair Francis, 2021/12/19
- [PULL 11/88] target/riscv: rvv-1.0: add mstatus VS field, Alistair Francis, 2021/12/19
- [PULL 12/88] target/riscv: rvv-1.0: set mstatus.SD bit if mstatus.VS is dirty, Alistair Francis, 2021/12/19
- [PULL 10/88] target/riscv: Use FIELD_EX32() to extract wd field, Alistair Francis, 2021/12/19
- [PULL 13/88] target/riscv: rvv-1.0: add sstatus VS field, Alistair Francis, 2021/12/19
- [PULL 14/88] target/riscv: rvv-1.0: introduce writable misa.v field, Alistair Francis, 2021/12/19
- [PULL 15/88] target/riscv: rvv-1.0: add translation-time vector context status, Alistair Francis, 2021/12/19
- [PULL 17/88] target/riscv: rvv-1.0: add vcsr register,
Alistair Francis <=
- [PULL 16/88] target/riscv: rvv-1.0: remove rvv related codes from fcsr registers, Alistair Francis, 2021/12/19
- [PULL 18/88] target/riscv: rvv-1.0: add vlenb register, Alistair Francis, 2021/12/19
- [PULL 19/88] target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers, Alistair Francis, 2021/12/19
- [PULL 21/88] target/riscv: rvv-1.0: add fractional LMUL, Alistair Francis, 2021/12/19
- [PULL 20/88] target/riscv: rvv-1.0: remove MLEN calculations, Alistair Francis, 2021/12/19
- [PULL 22/88] target/riscv: rvv-1.0: add VMA and VTA, Alistair Francis, 2021/12/19
- [PULL 23/88] target/riscv: rvv-1.0: update check functions, Alistair Francis, 2021/12/19
- [PULL 24/88] target/riscv: introduce more imm value modes in translator functions, Alistair Francis, 2021/12/19
- [PULL 25/88] target/riscv: rvv:1.0: add translation-time nan-box helper function, Alistair Francis, 2021/12/19
- [PULL 26/88] target/riscv: rvv-1.0: remove amo operations instructions, Alistair Francis, 2021/12/19