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[PULL 18/33] tests/tcg: Add arm and aarch64 pc alignment tests
From: |
Peter Maydell |
Subject: |
[PULL 18/33] tests/tcg: Add arm and aarch64 pc alignment tests |
Date: |
Wed, 15 Dec 2021 10:40:34 +0000 |
From: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
tests/tcg/aarch64/pcalign-a64.c | 37 +++++++++++++++++++++++++
tests/tcg/arm/pcalign-a32.c | 46 +++++++++++++++++++++++++++++++
tests/tcg/aarch64/Makefile.target | 4 +--
tests/tcg/arm/Makefile.target | 4 +++
4 files changed, 89 insertions(+), 2 deletions(-)
create mode 100644 tests/tcg/aarch64/pcalign-a64.c
create mode 100644 tests/tcg/arm/pcalign-a32.c
diff --git a/tests/tcg/aarch64/pcalign-a64.c b/tests/tcg/aarch64/pcalign-a64.c
new file mode 100644
index 00000000000..6b9277f919f
--- /dev/null
+++ b/tests/tcg/aarch64/pcalign-a64.c
@@ -0,0 +1,37 @@
+/* Test PC misalignment exception */
+
+#include <assert.h>
+#include <signal.h>
+#include <stdlib.h>
+#include <stdio.h>
+
+static void *expected;
+
+static void sigbus(int sig, siginfo_t *info, void *vuc)
+{
+ assert(info->si_code == BUS_ADRALN);
+ assert(info->si_addr == expected);
+ exit(EXIT_SUCCESS);
+}
+
+int main()
+{
+ void *tmp;
+
+ struct sigaction sa = {
+ .sa_sigaction = sigbus,
+ .sa_flags = SA_SIGINFO
+ };
+
+ if (sigaction(SIGBUS, &sa, NULL) < 0) {
+ perror("sigaction");
+ return EXIT_FAILURE;
+ }
+
+ asm volatile("adr %0, 1f + 1\n\t"
+ "str %0, %1\n\t"
+ "br %0\n"
+ "1:"
+ : "=&r"(tmp), "=m"(expected));
+ abort();
+}
diff --git a/tests/tcg/arm/pcalign-a32.c b/tests/tcg/arm/pcalign-a32.c
new file mode 100644
index 00000000000..3c9c8cc97b1
--- /dev/null
+++ b/tests/tcg/arm/pcalign-a32.c
@@ -0,0 +1,46 @@
+/* Test PC misalignment exception */
+
+#ifdef __thumb__
+#error "This test must be compiled for ARM"
+#endif
+
+#include <assert.h>
+#include <signal.h>
+#include <stdlib.h>
+#include <stdio.h>
+
+static void *expected;
+
+static void sigbus(int sig, siginfo_t *info, void *vuc)
+{
+ assert(info->si_code == BUS_ADRALN);
+ assert(info->si_addr == expected);
+ exit(EXIT_SUCCESS);
+}
+
+int main()
+{
+ void *tmp;
+
+ struct sigaction sa = {
+ .sa_sigaction = sigbus,
+ .sa_flags = SA_SIGINFO
+ };
+
+ if (sigaction(SIGBUS, &sa, NULL) < 0) {
+ perror("sigaction");
+ return EXIT_FAILURE;
+ }
+
+ asm volatile("adr %0, 1f + 2\n\t"
+ "str %0, %1\n\t"
+ "bx %0\n"
+ "1:"
+ : "=&r"(tmp), "=m"(expected));
+
+ /*
+ * From v8, it is CONSTRAINED UNPREDICTABLE whether BXWritePC aligns
+ * the address or not. If so, we can legitimately fall through.
+ */
+ return EXIT_SUCCESS;
+}
diff --git a/tests/tcg/aarch64/Makefile.target
b/tests/tcg/aarch64/Makefile.target
index 2c05c90d170..1d967901bd2 100644
--- a/tests/tcg/aarch64/Makefile.target
+++ b/tests/tcg/aarch64/Makefile.target
@@ -8,8 +8,8 @@ VPATH += $(ARM_SRC)
AARCH64_SRC=$(SRC_PATH)/tests/tcg/aarch64
VPATH += $(AARCH64_SRC)
-# Float-convert Tests
-AARCH64_TESTS=fcvt
+# Base architecture tests
+AARCH64_TESTS=fcvt pcalign-a64
fcvt: LDFLAGS+=-lm
diff --git a/tests/tcg/arm/Makefile.target b/tests/tcg/arm/Makefile.target
index 5ab59ed6ce1..f509d823d4f 100644
--- a/tests/tcg/arm/Makefile.target
+++ b/tests/tcg/arm/Makefile.target
@@ -29,6 +29,10 @@ run-fcvt: fcvt
$(call run-test,fcvt,$(QEMU) $<,"$< on $(TARGET_NAME)")
$(call diff-out,fcvt,$(ARM_SRC)/fcvt.ref)
+# PC alignment test
+ARM_TESTS += pcalign-a32
+pcalign-a32: CFLAGS+=-marm
+
ifeq ($(CONFIG_ARM_COMPATIBLE_SEMIHOSTING),y)
# Semihosting smoke test for linux-user
--
2.25.1
- [PULL 10/33] target/arm: Hoist pc_next to a local variable in arm_tr_translate_insn, (continued)
- [PULL 10/33] target/arm: Hoist pc_next to a local variable in arm_tr_translate_insn, Peter Maydell, 2021/12/15
- [PULL 12/33] target/arm: Split arm_pre_translate_insn, Peter Maydell, 2021/12/15
- [PULL 14/33] target/arm: Split compute_fsr_fsc out of arm_deliver_fault, Peter Maydell, 2021/12/15
- [PULL 09/33] target/arm: Hoist pc_next to a local variable in aarch64_tr_translate_insn, Peter Maydell, 2021/12/15
- [PULL 15/33] target/arm: Take an exception if PC is misaligned, Peter Maydell, 2021/12/15
- [PULL 16/33] target/arm: Assert thumb pc is aligned, Peter Maydell, 2021/12/15
- [PULL 17/33] target/arm: Suppress bp for exceptions with more priority, Peter Maydell, 2021/12/15
- [PULL 20/33] include/hw/i386: Don't include qemu-common.h in .h files, Peter Maydell, 2021/12/15
- [PULL 21/33] target/hexagon/cpu.h: don't include qemu-common.h, Peter Maydell, 2021/12/15
- [PULL 13/33] target/arm: Advance pc for arch single-step exception, Peter Maydell, 2021/12/15
- [PULL 18/33] tests/tcg: Add arm and aarch64 pc alignment tests,
Peter Maydell <=
- [PULL 19/33] target/i386: Use assert() to sanity-check b1 in SSE decode, Peter Maydell, 2021/12/15
- [PULL 24/33] target/arm: Correct calculation of tlb range invalidate length, Peter Maydell, 2021/12/15
- [PULL 27/33] hw/arm/virt: Remove device tree restriction for virtio-iommu, Peter Maydell, 2021/12/15
- [PULL 28/33] hw/arm/virt: Reject instantiation of multiple IOMMUs, Peter Maydell, 2021/12/15
- [PULL 08/33] hw/intc/arm_gicv3: Introduce CONFIG_ARM_GIC_TCG Kconfig selector, Peter Maydell, 2021/12/15
- [PULL 32/33] tests/acpi: add expected blobs for VIOT test on q35 machine, Peter Maydell, 2021/12/15
- [PULL 25/33] hw/net: npcm7xx_emc fix missing queue_flush, Peter Maydell, 2021/12/15
- [PULL 26/33] hw/arm/virt-acpi-build: Add VIOT table for virtio-iommu, Peter Maydell, 2021/12/15
- [PULL 22/33] target/rx/cpu.h: Don't include qemu-common.h, Peter Maydell, 2021/12/15
- [PULL 23/33] hw/arm: Don't include qemu-common.h unnecessarily, Peter Maydell, 2021/12/15