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[PULL 17/33] target/arm: Suppress bp for exceptions with more priority
From: |
Peter Maydell |
Subject: |
[PULL 17/33] target/arm: Suppress bp for exceptions with more priority |
Date: |
Wed, 15 Dec 2021 10:40:33 +0000 |
From: Richard Henderson <richard.henderson@linaro.org>
Both single-step and pc alignment faults have priority over
breakpoint exceptions.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/debug_helper.c | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c
index 2983e36dd33..32f3caec238 100644
--- a/target/arm/debug_helper.c
+++ b/target/arm/debug_helper.c
@@ -220,6 +220,7 @@ bool arm_debug_check_breakpoint(CPUState *cs)
{
ARMCPU *cpu = ARM_CPU(cs);
CPUARMState *env = &cpu->env;
+ target_ulong pc;
int n;
/*
@@ -231,6 +232,28 @@ bool arm_debug_check_breakpoint(CPUState *cs)
return false;
}
+ /*
+ * Single-step exceptions have priority over breakpoint exceptions.
+ * If single-step state is active-pending, suppress the bp.
+ */
+ if (arm_singlestep_active(env) && !(env->pstate & PSTATE_SS)) {
+ return false;
+ }
+
+ /*
+ * PC alignment faults have priority over breakpoint exceptions.
+ */
+ pc = is_a64(env) ? env->pc : env->regs[15];
+ if ((is_a64(env) || !env->thumb) && (pc & 3) != 0) {
+ return false;
+ }
+
+ /*
+ * Instruction aborts have priority over breakpoint exceptions.
+ * TODO: We would need to look up the page for PC and verify that
+ * it is present and executable.
+ */
+
for (n = 0; n < ARRAY_SIZE(env->cpu_breakpoint); n++) {
if (bp_wp_matches(cpu, n, false)) {
return true;
--
2.25.1
- [PULL 04/33] docs: aspeed: Give an example of booting a kernel, (continued)
- [PULL 04/33] docs: aspeed: Give an example of booting a kernel, Peter Maydell, 2021/12/15
- [PULL 11/33] target/arm: Hoist pc_next to a local variable in thumb_tr_translate_insn, Peter Maydell, 2021/12/15
- [PULL 06/33] Fix STM32F2XX USART data register readout, Peter Maydell, 2021/12/15
- [PULL 05/33] docs: aspeed: ADC is now modelled, Peter Maydell, 2021/12/15
- [PULL 10/33] target/arm: Hoist pc_next to a local variable in arm_tr_translate_insn, Peter Maydell, 2021/12/15
- [PULL 12/33] target/arm: Split arm_pre_translate_insn, Peter Maydell, 2021/12/15
- [PULL 14/33] target/arm: Split compute_fsr_fsc out of arm_deliver_fault, Peter Maydell, 2021/12/15
- [PULL 09/33] target/arm: Hoist pc_next to a local variable in aarch64_tr_translate_insn, Peter Maydell, 2021/12/15
- [PULL 15/33] target/arm: Take an exception if PC is misaligned, Peter Maydell, 2021/12/15
- [PULL 16/33] target/arm: Assert thumb pc is aligned, Peter Maydell, 2021/12/15
- [PULL 17/33] target/arm: Suppress bp for exceptions with more priority,
Peter Maydell <=
- [PULL 20/33] include/hw/i386: Don't include qemu-common.h in .h files, Peter Maydell, 2021/12/15
- [PULL 21/33] target/hexagon/cpu.h: don't include qemu-common.h, Peter Maydell, 2021/12/15
- [PULL 13/33] target/arm: Advance pc for arch single-step exception, Peter Maydell, 2021/12/15
- [PULL 18/33] tests/tcg: Add arm and aarch64 pc alignment tests, Peter Maydell, 2021/12/15
- [PULL 19/33] target/i386: Use assert() to sanity-check b1 in SSE decode, Peter Maydell, 2021/12/15
- [PULL 24/33] target/arm: Correct calculation of tlb range invalidate length, Peter Maydell, 2021/12/15
- [PULL 27/33] hw/arm/virt: Remove device tree restriction for virtio-iommu, Peter Maydell, 2021/12/15
- [PULL 28/33] hw/arm/virt: Reject instantiation of multiple IOMMUs, Peter Maydell, 2021/12/15
- [PULL 08/33] hw/intc/arm_gicv3: Introduce CONFIG_ARM_GIC_TCG Kconfig selector, Peter Maydell, 2021/12/15
- [PULL 32/33] tests/acpi: add expected blobs for VIOT test on q35 machine, Peter Maydell, 2021/12/15