Re: [PATCH v5 09/18] target/riscv: accessors to registers upper part and

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Re: [PATCH v5 09/18] target/riscv: accessors to registers upper part and

From:	Richard Henderson
Subject:	Re: [PATCH v5 09/18] target/riscv: accessors to registers upper part and 128-bit load/store
Date:	Mon, 15 Nov 2021 09:29:45 +0100
User-agent:	Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.14.0

On 11/12/21 3:58 PM, Frédéric Pétrot wrote:

+/* Compute only 64-bit addresses to use the address translation mechanism */
+static bool gen_load_i128(DisasContext *ctx, arg_lb *a, MemOp memop)
+{
+    TCGv src1l = get_gpr(ctx, a->rs1, EXT_NONE);
+    TCGv destl = dest_gpr(ctx, a->rd);
+    TCGv desth = dest_gprh(ctx, a->rd);
+    TCGv addrl = tcg_temp_new();
+
+    tcg_gen_addi_tl(addrl, src1l, a->imm);
+
+    if (memop != MO_TEUO) {


It is perhaps clearer as (memop & MO_SIZE) <= MO_64.

+        tcg_gen_qemu_ld_tl(memop & MO_BSWAP ? desth : destl, addrl,
+                           ctx->mem_idx, MO_TEUQ);


This isn't correct.  MO_BSWAP is related to the host, not the guest.

You want

        (memop & MO_BSWAP) == MO_LE ? destl : desth

Are there any big-endian RISC-V though?

+static bool gen_store_i128(DisasContext *ctx, arg_sb *a, MemOp memop)
+{
+    TCGv src1l = get_gpr(ctx, a->rs1, EXT_NONE);
+    TCGv src2l = get_gpr(ctx, a->rs2, EXT_NONE);
+    TCGv src2h = get_gprh(ctx, a->rs2);
+    TCGv addrl = tcg_temp_new();
+
+    tcg_gen_addi_tl(addrl, src1l, a->imm);
+
+    if (memop != MO_TEUO) {
+        tcg_gen_qemu_st_tl(src2l, addrl, ctx->mem_idx, memop);
+    } else {
+        tcg_gen_qemu_st_tl(memop & MO_BSWAP ? src2h : src2l, addrl,
+            ctx->mem_idx, MO_TEUQ);


Likewise.


r~

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[PATCH v5 05/18] target/riscv: separation of bitwise logic and arithmetic helpers, (continued)
- [PATCH v5 05/18] target/riscv: separation of bitwise logic and arithmetic helpers, Frédéric Pétrot, 2021/11/12
  - Re: [PATCH v5 05/18] target/riscv: separation of bitwise logic and arithmetic helpers, Alistair Francis, 2021/11/23
- [PATCH v5 15/18] target/riscv: adding high part of some csrs, Frédéric Pétrot, 2021/11/12
- [PATCH v5 17/18] target/riscv: modification of the trans_csrxx for 128-bit support, Frédéric Pétrot, 2021/11/12
- [PATCH v5 16/18] target/riscv: helper functions to wrap calls to 128-bit csr insns, Frédéric Pétrot, 2021/11/12
- [PATCH v5 14/18] target/riscv: support for 128-bit M extension, Frédéric Pétrot, 2021/11/12
- [PATCH v5 12/18] target/riscv: support for 128-bit shift instructions, Frédéric Pétrot, 2021/11/12
- [PATCH v5 18/18] target/riscv: actual functions to realize crs 128-bit insns, Frédéric Pétrot, 2021/11/12
- [PATCH v5 13/18] target/riscv: support for 128-bit arithmetic instructions, Frédéric Pétrot, 2021/11/12
- [PATCH v5 09/18] target/riscv: accessors to registers upper part and 128-bit load/store, Frédéric Pétrot, 2021/11/12
  - Re: [PATCH v5 09/18] target/riscv: accessors to registers upper part and 128-bit load/store, Richard Henderson <=
    - Re: [PATCH v5 09/18] target/riscv: accessors to registers upper part and 128-bit load/store, Frédéric Pétrot, 2021/11/16
- [PATCH v5 10/18] target/riscv: support for 128-bit bitwise instructions, Frédéric Pétrot, 2021/11/12
  - Re: [PATCH v5 10/18] target/riscv: support for 128-bit bitwise instructions, Richard Henderson, 2021/11/15
  - Re: [PATCH v5 10/18] target/riscv: support for 128-bit bitwise instructions, Alistair Francis, 2021/11/24

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