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Re: [PATCH v5 10/18] target/riscv: support for 128-bit bitwise instructi
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From: |
Alistair Francis |
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Subject: |
Re: [PATCH v5 10/18] target/riscv: support for 128-bit bitwise instructions |
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Date: |
Wed, 24 Nov 2021 16:13:40 +1000 |
On Sat, Nov 13, 2021 at 1:20 AM Frédéric Pétrot
<frederic.petrot@univ-grenoble-alpes.fr> wrote:
>
> The 128-bit bitwise instructions do not need any function prototype change
> as the functions can be applied independently on the lower and upper part of
> the registers.
>
> Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
> Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/translate.c | 21 +++++++++++++++++++--
> 1 file changed, 19 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 554cf05084..508ae87985 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -448,7 +448,15 @@ static bool gen_logic_imm_fn(DisasContext *ctx, arg_i *a,
>
> func(dest, src1, a->imm);
>
> - gen_set_gpr(ctx, a->rd, dest);
> + if (get_xl(ctx) == MXL_RV128) {
> + TCGv src1h = get_gprh(ctx, a->rs1);
> + TCGv desth = dest_gprh(ctx, a->rd);
> +
> + func(desth, src1h, -(a->imm < 0));
> + gen_set_gpr128(ctx, a->rd, dest, desth);
> + } else {
> + gen_set_gpr(ctx, a->rd, dest);
> + }
>
> return true;
> }
> @@ -462,7 +470,16 @@ static bool gen_logic(DisasContext *ctx, arg_r *a,
>
> func(dest, src1, src2);
>
> - gen_set_gpr(ctx, a->rd, dest);
> + if (get_xl(ctx) == MXL_RV128) {
> + TCGv src1h = get_gprh(ctx, a->rs1);
> + TCGv src2h = get_gprh(ctx, a->rs2);
> + TCGv desth = dest_gprh(ctx, a->rd);
> +
> + func(desth, src1h, src2h);
> + gen_set_gpr128(ctx, a->rd, dest, desth);
> + } else {
> + gen_set_gpr(ctx, a->rd, dest);
> + }
>
> return true;
> }
> --
> 2.33.1
>
>
- [PATCH v5 16/18] target/riscv: helper functions to wrap calls to 128-bit csr insns, (continued)
- [PATCH v5 16/18] target/riscv: helper functions to wrap calls to 128-bit csr insns, Frédéric Pétrot, 2021/11/12
- [PATCH v5 14/18] target/riscv: support for 128-bit M extension, Frédéric Pétrot, 2021/11/12
- [PATCH v5 12/18] target/riscv: support for 128-bit shift instructions, Frédéric Pétrot, 2021/11/12
- [PATCH v5 18/18] target/riscv: actual functions to realize crs 128-bit insns, Frédéric Pétrot, 2021/11/12
- [PATCH v5 13/18] target/riscv: support for 128-bit arithmetic instructions, Frédéric Pétrot, 2021/11/12
- [PATCH v5 09/18] target/riscv: accessors to registers upper part and 128-bit load/store, Frédéric Pétrot, 2021/11/12
- [PATCH v5 10/18] target/riscv: support for 128-bit bitwise instructions, Frédéric Pétrot, 2021/11/12