Re: [PATCH v5 05/18] target/riscv: separation of bitwise logic and arithmetic helpers

[Alistair Francis]

On Sat, Nov 13, 2021 at 1:11 AM Frédéric Pétrot
<frederic.petrot@univ-grenoble-alpes.fr> wrote:
>
> Introduction of a gen_logic function for bitwise logic to implement
> instructions in which not propagation of information occurs between bits and
> use of this function on the bitwise instructions.
>
> Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
> Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/translate.c                | 27 +++++++++++++++++++++++++
>  target/riscv/insn_trans/trans_rvb.c.inc |  6 +++---
>  target/riscv/insn_trans/trans_rvi.c.inc | 12 +++++------
>  3 files changed, 36 insertions(+), 9 deletions(-)
>
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index d98bde9b6b..b4278a6a92 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -400,6 +400,33 @@ static int ex_rvc_shifti(DisasContext *ctx, int imm)
>  /* Include the auto-generated decoder for 32 bit insn */
>  #include "decode-insn32.c.inc"
>
> +static bool gen_logic_imm_fn(DisasContext *ctx, arg_i *a,
> +                             void (*func)(TCGv, TCGv, target_long))
> +{
> +    TCGv dest = dest_gpr(ctx, a->rd);
> +    TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
> +
> +    func(dest, src1, a->imm);
> +
> +    gen_set_gpr(ctx, a->rd, dest);
> +
> +    return true;
> +}
> +
> +static bool gen_logic(DisasContext *ctx, arg_r *a,
> +                      void (*func)(TCGv, TCGv, TCGv))
> +{
> +    TCGv dest = dest_gpr(ctx, a->rd);
> +    TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
> +    TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
> +
> +    func(dest, src1, src2);
> +
> +    gen_set_gpr(ctx, a->rd, dest);
> +
> +    return true;
> +}
> +
>  static bool gen_arith_imm_fn(DisasContext *ctx, arg_i *a, DisasExtend ext,
>                               void (*func)(TCGv, TCGv, target_long))
>  {
> diff --git a/target/riscv/insn_trans/trans_rvb.c.inc 
> b/target/riscv/insn_trans/trans_rvb.c.inc
> index c8d31907c5..de2cd613b1 100644
> --- a/target/riscv/insn_trans/trans_rvb.c.inc
> +++ b/target/riscv/insn_trans/trans_rvb.c.inc
> @@ -86,19 +86,19 @@ static bool trans_cpop(DisasContext *ctx, arg_cpop *a)
>  static bool trans_andn(DisasContext *ctx, arg_andn *a)
>  {
>      REQUIRE_ZBB(ctx);
> -    return gen_arith(ctx, a, EXT_NONE, tcg_gen_andc_tl);
> +    return gen_logic(ctx, a, tcg_gen_andc_tl);
>  }
>
>  static bool trans_orn(DisasContext *ctx, arg_orn *a)
>  {
>      REQUIRE_ZBB(ctx);
> -    return gen_arith(ctx, a, EXT_NONE, tcg_gen_orc_tl);
> +    return gen_logic(ctx, a, tcg_gen_orc_tl);
>  }
>
>  static bool trans_xnor(DisasContext *ctx, arg_xnor *a)
>  {
>      REQUIRE_ZBB(ctx);
> -    return gen_arith(ctx, a, EXT_NONE, tcg_gen_eqv_tl);
> +    return gen_logic(ctx, a, tcg_gen_eqv_tl);
>  }
>
>  static bool trans_min(DisasContext *ctx, arg_min *a)
> diff --git a/target/riscv/insn_trans/trans_rvi.c.inc 
> b/target/riscv/insn_trans/trans_rvi.c.inc
> index 4a2aefe3a5..51607b3d40 100644
> --- a/target/riscv/insn_trans/trans_rvi.c.inc
> +++ b/target/riscv/insn_trans/trans_rvi.c.inc
> @@ -252,17 +252,17 @@ static bool trans_sltiu(DisasContext *ctx, arg_sltiu *a)
>
>  static bool trans_xori(DisasContext *ctx, arg_xori *a)
>  {
> -    return gen_arith_imm_fn(ctx, a, EXT_NONE, tcg_gen_xori_tl);
> +    return gen_logic_imm_fn(ctx, a, tcg_gen_xori_tl);
>  }
>
>  static bool trans_ori(DisasContext *ctx, arg_ori *a)
>  {
> -    return gen_arith_imm_fn(ctx, a, EXT_NONE, tcg_gen_ori_tl);
> +    return gen_logic_imm_fn(ctx, a, tcg_gen_ori_tl);
>  }
>
>  static bool trans_andi(DisasContext *ctx, arg_andi *a)
>  {
> -    return gen_arith_imm_fn(ctx, a, EXT_NONE, tcg_gen_andi_tl);
> +    return gen_logic_imm_fn(ctx, a, tcg_gen_andi_tl);
>  }
>
>  static bool trans_slli(DisasContext *ctx, arg_slli *a)
> @@ -319,7 +319,7 @@ static bool trans_sltu(DisasContext *ctx, arg_sltu *a)
>
>  static bool trans_xor(DisasContext *ctx, arg_xor *a)
>  {
> -    return gen_arith(ctx, a, EXT_NONE, tcg_gen_xor_tl);
> +    return gen_logic(ctx, a, tcg_gen_xor_tl);
>  }
>
>  static bool trans_srl(DisasContext *ctx, arg_srl *a)
> @@ -334,12 +334,12 @@ static bool trans_sra(DisasContext *ctx, arg_sra *a)
>
>  static bool trans_or(DisasContext *ctx, arg_or *a)
>  {
> -    return gen_arith(ctx, a, EXT_NONE, tcg_gen_or_tl);
> +    return gen_logic(ctx, a, tcg_gen_or_tl);
>  }
>
>  static bool trans_and(DisasContext *ctx, arg_and *a)
>  {
> -    return gen_arith(ctx, a, EXT_NONE, tcg_gen_and_tl);
> +    return gen_logic(ctx, a, tcg_gen_and_tl);
>  }
>
>  static bool trans_addiw(DisasContext *ctx, arg_addiw *a)
> --
> 2.33.1
>
>