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[PULL 31/41] target/mips: Convert CFCMSA opcode to decodetree
From: |
Philippe Mathieu-Daudé |
Subject: |
[PULL 31/41] target/mips: Convert CFCMSA opcode to decodetree |
Date: |
Tue, 2 Nov 2021 14:42:30 +0100 |
Convert the CFCMSA (Copy From Control MSA register) opcode
to decodetree. Since it overlaps with the SPLATI opcode,
use a decodetree overlap group.
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211028210843.2120802-29-f4bug@amsat.org>
---
target/mips/tcg/msa.decode | 5 ++++-
target/mips/tcg/msa_translate.c | 27 +++++++++++++++++++--------
2 files changed, 23 insertions(+), 9 deletions(-)
diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
index d1b6a63b526..de8153a89bf 100644
--- a/target/mips/tcg/msa.decode
+++ b/target/mips/tcg/msa.decode
@@ -168,7 +168,10 @@ BNZ 010001 111 .. ..... ................
@bz
HSUB_U 011110 111.. ..... ..... ..... 010101 @3r
SLDI 011110 0000 ...... ..... ..... 011001 @elm_df
- SPLATI 011110 0001 ...... ..... ..... 011001 @elm_df
+ {
+ CFCMSA 011110 0001111110 ..... ..... 011001 @elm
+ SPLATI 011110 0001 ...... ..... ..... 011001 @elm_df
+ }
{
MOVE_V 011110 0010111110 ..... ..... 011001 @elm
COPY_S 011110 0010 ...... ..... ..... 011001 @elm_df
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index ea572413ed6..764b33741aa 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -45,7 +45,6 @@ enum {
enum {
/* ELM instructions df(bits 21..16) = _b, _h, _w, _d */
OPC_CTCMSA = (0x0 << 22) | (0x3E << 16) | OPC_MSA_ELM,
- OPC_CFCMSA = (0x1 << 22) | (0x3E << 16) | OPC_MSA_ELM,
};
static const char msaregnames[][6] = {
@@ -551,7 +550,6 @@ static void gen_msa_elm_3e(DisasContext *ctx)
uint8_t source = (ctx->opcode >> 11) & 0x1f;
uint8_t dest = (ctx->opcode >> 6) & 0x1f;
TCGv telm = tcg_temp_new();
- TCGv_i32 tsr = tcg_const_i32(source);
TCGv_i32 tdt = tcg_const_i32(dest);
switch (MASK_MSA_ELM_DF3E(ctx->opcode)) {
@@ -559,10 +557,6 @@ static void gen_msa_elm_3e(DisasContext *ctx)
gen_load_gpr(telm, source);
gen_helper_msa_ctcmsa(cpu_env, telm, tdt);
break;
- case OPC_CFCMSA:
- gen_helper_msa_cfcmsa(telm, cpu_env, tsr);
- gen_store_gpr(telm, dest);
- break;
default:
MIPS_INVAL("MSA instruction");
gen_reserved_instruction(ctx);
@@ -571,7 +565,24 @@ static void gen_msa_elm_3e(DisasContext *ctx)
tcg_temp_free(telm);
tcg_temp_free_i32(tdt);
- tcg_temp_free_i32(tsr);
+}
+
+static bool trans_CFCMSA(DisasContext *ctx, arg_msa_elm *a)
+{
+ TCGv telm;
+
+ if (!check_msa_enabled(ctx)) {
+ return true;
+ }
+
+ telm = tcg_temp_new();
+
+ gen_helper_msa_cfcmsa(telm, cpu_env, tcg_constant_i32(a->ws));
+ gen_store_gpr(telm, a->wd);
+
+ tcg_temp_free(telm);
+
+ return true;
}
static bool trans_msa_elm(DisasContext *ctx, arg_msa_elm_df *a,
@@ -663,7 +674,7 @@ static void gen_msa_elm(DisasContext *ctx)
uint8_t dfn = (ctx->opcode >> 16) & 0x3f;
if (dfn == 0x3E) {
- /* CTCMSA, CFCMSA */
+ /* CTCMSA */
gen_msa_elm_3e(ctx);
return;
} else {
--
2.31.1
- [PULL 21/41] target/mips: Convert MSA 3RF instruction format to decodetree (DF_HALF), (continued)
- [PULL 21/41] target/mips: Convert MSA 3RF instruction format to decodetree (DF_HALF), Philippe Mathieu-Daudé, 2021/11/02
- [PULL 22/41] target/mips: Convert MSA 3RF instruction format to decodetree (DF_WORD), Philippe Mathieu-Daudé, 2021/11/02
- [PULL 23/41] target/mips: Convert MSA 3R instruction format to decodetree (part 1/4), Philippe Mathieu-Daudé, 2021/11/02
- [PULL 24/41] target/mips: Convert MSA 3R instruction format to decodetree (part 2/4), Philippe Mathieu-Daudé, 2021/11/02
- [PULL 25/41] target/mips: Convert MSA 3R instruction format to decodetree (part 3/4), Philippe Mathieu-Daudé, 2021/11/02
- [PULL 26/41] target/mips: Convert MSA 3R instruction format to decodetree (part 4/4), Philippe Mathieu-Daudé, 2021/11/02
- [PULL 27/41] target/mips: Convert MSA ELM instruction format to decodetree, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 28/41] target/mips: Convert MSA COPY_U opcode to decodetree, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 29/41] target/mips: Convert MSA COPY_S and INSERT opcodes to decodetree, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 30/41] target/mips: Convert MSA MOVE.V opcode to decodetree, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 31/41] target/mips: Convert CFCMSA opcode to decodetree,
Philippe Mathieu-Daudé <=
- [PULL 32/41] target/mips: Convert CTCMSA opcode to decodetree, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 33/41] target/mips: Remove generic MSA opcode, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 34/41] target/mips: Remove one MSA unnecessary decodetree overlap group, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 36/41] target/mips: Remove obsolete FCR0_HAS2008 comment on P5600 CPU, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 35/41] target/mips: Fix Loongson-3A4000 MSAIR config register, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 37/41] usb/uhci: Misc clean up, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 38/41] usb/uhci: Disallow user creating a vt82c686-uhci-pci device, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 39/41] usb/uhci: Replace pci_set_irq with qemu_set_irq, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 40/41] hw/usb/vt82c686-uhci-pci: Use ISA instead of PCI interrupts, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 41/41] Revert "elf: Relax MIPS' elf_check_arch() to accept EM_NANOMIPS too", Philippe Mathieu-Daudé, 2021/11/02