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[PULL 23/41] target/mips: Convert MSA 3R instruction format to decodetre
From: |
Philippe Mathieu-Daudé |
Subject: |
[PULL 23/41] target/mips: Convert MSA 3R instruction format to decodetree (part 1/4) |
Date: |
Tue, 2 Nov 2021 14:42:22 +0100 |
Convert 3-register operations to decodetree.
Since the 'data format' field is a constant value, use
tcg_constant_i32() instead of a TCG temporary.
Note, the format definition could be named @3rf_b (for
3R with a df field BYTE-based) but since the instruction
class is named '3R', we simply call the format @3r to
ease reviewing the msa.decode file.
However we directly call the trans_msa_3rf() function,
which handles the BYTE-based df field.
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211028210843.2120802-21-f4bug@amsat.org>
---
target/mips/tcg/msa.decode | 6 ++++++
target/mips/tcg/msa_translate.c | 17 +++++------------
2 files changed, 11 insertions(+), 12 deletions(-)
diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
index 1d6ada4c142..4b14acce26f 100644
--- a/target/mips/tcg/msa.decode
+++ b/target/mips/tcg/msa.decode
@@ -32,6 +32,7 @@
@vec ...... ..... wt:5 ws:5 wd:5 ...... &msa_r df=0
@2r ...... ........ df:2 ws:5 wd:5 ...... &msa_r wt=0
@2rf ...... ......... . ws:5 wd:5 ...... &msa_r wt=0
df=%2r_df_w
+@3r ...... ... df:2 wt:5 ws:5 wd:5 ...... &msa_r
@3rf_h ...... .... . wt:5 ws:5 wd:5 ...... &msa_r df=%3r_df_h
@3rf_w ...... .... . wt:5 ws:5 wd:5 ...... &msa_r df=%3r_df_w
@u5 ...... ... df:2 sa:5 ws:5 wd:5 ...... &msa_i
@@ -88,6 +89,11 @@ BNZ 010001 111 .. ..... ................
@bz
SRARI 011110 010 ....... ..... ..... 001010 @bit
SRLRI 011110 011 ....... ..... ..... 001010 @bit
+ SLD 011110 000 .. ..... ..... ..... 010100 @3r
+ SPLAT 011110 001 .. ..... ..... ..... 010100 @3r
+
+ VSHF 011110 000 .. ..... ..... ..... 010101 @3r
+
FCAF 011110 0000 . ..... ..... ..... 011010 @3rf_w
FCUN 011110 0001 . ..... ..... ..... 011010 @3rf_w
FCEQ 011110 0010 . ..... ..... ..... 011010 @3rf_w
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index 26d05a87c89..ddc0bd08ddf 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -58,15 +58,12 @@ enum {
OPC_SUBS_S_df = (0x0 << 23) | OPC_MSA_3R_11,
OPC_MULV_df = (0x0 << 23) | OPC_MSA_3R_12,
OPC_DOTP_S_df = (0x0 << 23) | OPC_MSA_3R_13,
- OPC_SLD_df = (0x0 << 23) | OPC_MSA_3R_14,
- OPC_VSHF_df = (0x0 << 23) | OPC_MSA_3R_15,
OPC_SRA_df = (0x1 << 23) | OPC_MSA_3R_0D,
OPC_SUBV_df = (0x1 << 23) | OPC_MSA_3R_0E,
OPC_ADDS_A_df = (0x1 << 23) | OPC_MSA_3R_10,
OPC_SUBS_U_df = (0x1 << 23) | OPC_MSA_3R_11,
OPC_MADDV_df = (0x1 << 23) | OPC_MSA_3R_12,
OPC_DOTP_U_df = (0x1 << 23) | OPC_MSA_3R_13,
- OPC_SPLAT_df = (0x1 << 23) | OPC_MSA_3R_14,
OPC_SRAR_df = (0x1 << 23) | OPC_MSA_3R_15,
OPC_SRL_df = (0x2 << 23) | OPC_MSA_3R_0D,
OPC_MAX_S_df = (0x2 << 23) | OPC_MSA_3R_0E,
@@ -505,6 +502,11 @@ TRANS(BMNZ_V, trans_msa_3r,
gen_helper_msa_bmnz_v);
TRANS(BMZ_V, trans_msa_3r, gen_helper_msa_bmz_v);
TRANS(BSEL_V, trans_msa_3r, gen_helper_msa_bsel_v);
+TRANS(SLD, trans_msa_3rf, gen_helper_msa_sld_df);
+TRANS(SPLAT, trans_msa_3rf, gen_helper_msa_splat_df);
+
+TRANS(VSHF, trans_msa_3rf, gen_helper_msa_vshf_df);
+
static void gen_msa_3r(DisasContext *ctx)
{
#define MASK_MSA_3R(op) (MASK_MSA_MINOR(op) | (op & (0x7 << 23)))
@@ -1255,12 +1257,6 @@ static void gen_msa_3r(DisasContext *ctx)
break;
}
break;
- case OPC_SLD_df:
- gen_helper_msa_sld_df(cpu_env, tdf, twd, tws, twt);
- break;
- case OPC_VSHF_df:
- gen_helper_msa_vshf_df(cpu_env, tdf, twd, tws, twt);
- break;
case OPC_SUBV_df:
switch (df) {
case DF_BYTE:
@@ -1293,9 +1289,6 @@ static void gen_msa_3r(DisasContext *ctx)
break;
}
break;
- case OPC_SPLAT_df:
- gen_helper_msa_splat_df(cpu_env, tdf, twd, tws, twt);
- break;
case OPC_SUBSUS_U_df:
switch (df) {
case DF_BYTE:
--
2.31.1
- [PULL 13/41] target/mips: Convert MSA BIT instruction format to decodetree, (continued)
- [PULL 13/41] target/mips: Convert MSA BIT instruction format to decodetree, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 14/41] target/mips: Convert MSA SHF opcode to decodetree, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 15/41] target/mips: Convert MSA I8 instruction format to decodetree, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 16/41] target/mips: Convert MSA load/store instruction format to decodetree, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 17/41] target/mips: Convert MSA 2RF instruction format to decodetree, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 18/41] target/mips: Convert MSA FILL opcode to decodetree, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 19/41] target/mips: Convert MSA 2R instruction format to decodetree, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 20/41] target/mips: Convert MSA VEC instruction format to decodetree, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 21/41] target/mips: Convert MSA 3RF instruction format to decodetree (DF_HALF), Philippe Mathieu-Daudé, 2021/11/02
- [PULL 22/41] target/mips: Convert MSA 3RF instruction format to decodetree (DF_WORD), Philippe Mathieu-Daudé, 2021/11/02
- [PULL 23/41] target/mips: Convert MSA 3R instruction format to decodetree (part 1/4),
Philippe Mathieu-Daudé <=
- [PULL 24/41] target/mips: Convert MSA 3R instruction format to decodetree (part 2/4), Philippe Mathieu-Daudé, 2021/11/02
- [PULL 25/41] target/mips: Convert MSA 3R instruction format to decodetree (part 3/4), Philippe Mathieu-Daudé, 2021/11/02
- [PULL 26/41] target/mips: Convert MSA 3R instruction format to decodetree (part 4/4), Philippe Mathieu-Daudé, 2021/11/02
- [PULL 27/41] target/mips: Convert MSA ELM instruction format to decodetree, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 28/41] target/mips: Convert MSA COPY_U opcode to decodetree, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 29/41] target/mips: Convert MSA COPY_S and INSERT opcodes to decodetree, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 30/41] target/mips: Convert MSA MOVE.V opcode to decodetree, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 31/41] target/mips: Convert CFCMSA opcode to decodetree, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 32/41] target/mips: Convert CTCMSA opcode to decodetree, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 33/41] target/mips: Remove generic MSA opcode, Philippe Mathieu-Daudé, 2021/11/02