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[PULL 25/41] target/mips: Convert MSA 3R instruction format to decodetre
From: |
Philippe Mathieu-Daudé |
Subject: |
[PULL 25/41] target/mips: Convert MSA 3R instruction format to decodetree (part 3/4) |
Date: |
Tue, 2 Nov 2021 14:42:24 +0100 |
Convert BINSL (Vector Bit Insert Left) and BINSR (Vector Bit
Insert Right) opcodes to decodetree.
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211028210843.2120802-23-f4bug@amsat.org>
---
target/mips/tcg/msa.decode | 3 +++
target/mips/tcg/msa_translate.c | 40 +++++----------------------------
2 files changed, 9 insertions(+), 34 deletions(-)
diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
index 0e2f474cde6..f2bacbaea86 100644
--- a/target/mips/tcg/msa.decode
+++ b/target/mips/tcg/msa.decode
@@ -89,6 +89,9 @@ BNZ 010001 111 .. ..... ................
@bz
SRARI 011110 010 ....... ..... ..... 001010 @bit
SRLRI 011110 011 ....... ..... ..... 001010 @bit
+ BINSL 011110 110.. ..... ..... ..... 001101 @3r
+ BINSR 011110 111.. ..... ..... ..... 001101 @3r
+
DOTP_S 011110 000.. ..... ..... ..... 010011 @3r
DOTP_U 011110 001.. ..... ..... ..... 010011 @3r
DPADD_S 011110 010.. ..... ..... ..... 010011 @3r
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index 5f3e1573e43..c52913632c5 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -91,12 +91,10 @@ enum {
OPC_ASUB_U_df = (0x5 << 23) | OPC_MSA_3R_11,
OPC_DIV_U_df = (0x5 << 23) | OPC_MSA_3R_12,
OPC_ILVR_df = (0x5 << 23) | OPC_MSA_3R_14,
- OPC_BINSL_df = (0x6 << 23) | OPC_MSA_3R_0D,
OPC_MAX_A_df = (0x6 << 23) | OPC_MSA_3R_0E,
OPC_AVER_S_df = (0x6 << 23) | OPC_MSA_3R_10,
OPC_MOD_S_df = (0x6 << 23) | OPC_MSA_3R_12,
OPC_ILVEV_df = (0x6 << 23) | OPC_MSA_3R_14,
- OPC_BINSR_df = (0x7 << 23) | OPC_MSA_3R_0D,
OPC_MIN_A_df = (0x7 << 23) | OPC_MSA_3R_0E,
OPC_AVER_U_df = (0x7 << 23) | OPC_MSA_3R_10,
OPC_MOD_U_df = (0x7 << 23) | OPC_MSA_3R_12,
@@ -245,6 +243,9 @@ typedef void gen_helper_piiii(TCGv_ptr, TCGv_i32, TCGv_i32,
TCGv_i32, TCGv_i32);
#define TRANS_DF_ii(NAME, trans_func, gen_func) \
TRANS_DF_x(ii, NAME, trans_func, gen_func)
+#define TRANS_DF_iii(NAME, trans_func, gen_func) \
+ TRANS_DF_x(iii, NAME, trans_func, gen_func)
+
#define TRANS_DF_iii_b(NAME, trans_func, gen_func) \
static gen_helper_piii * const NAME##_tab[4] = { \
NULL, gen_func##_h, gen_func##_w, gen_func##_d \
@@ -505,6 +506,9 @@ TRANS(BMNZ_V, trans_msa_3r,
gen_helper_msa_bmnz_v);
TRANS(BMZ_V, trans_msa_3r, gen_helper_msa_bmz_v);
TRANS(BSEL_V, trans_msa_3r, gen_helper_msa_bsel_v);
+TRANS_DF_iii(BINSL, trans_msa_3r, gen_helper_msa_binsl);
+TRANS_DF_iii(BINSR, trans_msa_3r, gen_helper_msa_binsr);
+
TRANS_DF_iii_b(DOTP_S, trans_msa_3r, gen_helper_msa_dotp_s);
TRANS_DF_iii_b(DOTP_U, trans_msa_3r, gen_helper_msa_dotp_u);
TRANS_DF_iii_b(DPADD_S, trans_msa_3r, gen_helper_msa_dpadd_s);
@@ -535,38 +539,6 @@ static void gen_msa_3r(DisasContext *ctx)
TCGv_i32 twt = tcg_const_i32(wt);
switch (MASK_MSA_3R(ctx->opcode)) {
- case OPC_BINSL_df:
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_binsl_b(cpu_env, twd, tws, twt);
- break;
- case DF_HALF:
- gen_helper_msa_binsl_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_binsl_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_binsl_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- case OPC_BINSR_df:
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_binsr_b(cpu_env, twd, tws, twt);
- break;
- case DF_HALF:
- gen_helper_msa_binsr_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_binsr_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_binsr_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
case OPC_BCLR_df:
switch (df) {
case DF_BYTE:
--
2.31.1
- [PULL 15/41] target/mips: Convert MSA I8 instruction format to decodetree, (continued)
- [PULL 15/41] target/mips: Convert MSA I8 instruction format to decodetree, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 16/41] target/mips: Convert MSA load/store instruction format to decodetree, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 17/41] target/mips: Convert MSA 2RF instruction format to decodetree, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 18/41] target/mips: Convert MSA FILL opcode to decodetree, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 19/41] target/mips: Convert MSA 2R instruction format to decodetree, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 20/41] target/mips: Convert MSA VEC instruction format to decodetree, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 21/41] target/mips: Convert MSA 3RF instruction format to decodetree (DF_HALF), Philippe Mathieu-Daudé, 2021/11/02
- [PULL 22/41] target/mips: Convert MSA 3RF instruction format to decodetree (DF_WORD), Philippe Mathieu-Daudé, 2021/11/02
- [PULL 23/41] target/mips: Convert MSA 3R instruction format to decodetree (part 1/4), Philippe Mathieu-Daudé, 2021/11/02
- [PULL 24/41] target/mips: Convert MSA 3R instruction format to decodetree (part 2/4), Philippe Mathieu-Daudé, 2021/11/02
- [PULL 25/41] target/mips: Convert MSA 3R instruction format to decodetree (part 3/4),
Philippe Mathieu-Daudé <=
- [PULL 26/41] target/mips: Convert MSA 3R instruction format to decodetree (part 4/4), Philippe Mathieu-Daudé, 2021/11/02
- [PULL 27/41] target/mips: Convert MSA ELM instruction format to decodetree, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 28/41] target/mips: Convert MSA COPY_U opcode to decodetree, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 29/41] target/mips: Convert MSA COPY_S and INSERT opcodes to decodetree, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 30/41] target/mips: Convert MSA MOVE.V opcode to decodetree, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 31/41] target/mips: Convert CFCMSA opcode to decodetree, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 32/41] target/mips: Convert CTCMSA opcode to decodetree, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 33/41] target/mips: Remove generic MSA opcode, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 34/41] target/mips: Remove one MSA unnecessary decodetree overlap group, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 36/41] target/mips: Remove obsolete FCR0_HAS2008 comment on P5600 CPU, Philippe Mathieu-Daudé, 2021/11/02