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[PATCH 13/13] target/riscv: Enable uxl field write
From: |
LIU Zhiwei |
Subject: |
[PATCH 13/13] target/riscv: Enable uxl field write |
Date: |
Mon, 1 Nov 2021 18:01:43 +0800 |
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
target/riscv/csr.c | 6 ++++--
target/riscv/insn_trans/trans_rvi.c.inc | 2 +-
2 files changed, 5 insertions(+), 3 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 9f41954894..471c10acf6 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -543,14 +543,16 @@ static RISCVException write_mstatus(CPURISCVState *env,
int csrno,
* add them to mstatush. For now, we just don't support it.
*/
mask |= MSTATUS_MPV | MSTATUS_GVA;
+ if ((val ^ mstatus) & MSTATUS64_UXL) {
+ mask |= MSTATUS64_UXL;
+ }
}
mstatus = (mstatus & ~mask) | (val & mask);
if (riscv_cpu_mxl(env) == MXL_RV64) {
- /* SXL and UXL fields are for now read only */
+ /* SXL fields are for now read only */
mstatus = set_field(mstatus, MSTATUS64_SXL, MXL_RV64);
- mstatus = set_field(mstatus, MSTATUS64_UXL, MXL_RV64);
}
env->mstatus = mstatus;
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc
b/target/riscv/insn_trans/trans_rvi.c.inc
index bd9d50bb94..880026f13d 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -475,7 +475,7 @@ static bool do_csrrw(DisasContext *ctx, int rd, int rc,
TCGv src, TCGv mask)
static bool trans_csrrw(DisasContext *ctx, arg_csrrw *a)
{
- TCGv src = get_gpr(ctx, a->rs1, EXT_NONE);
+ TCGv src = get_gpr(ctx, a->rs1, EXT_ZERO);
/*
* If rd == 0, the insn shall not read the csr, nor cause any of the
--
2.25.1
- Re: [PATCH 09/13] target/riscv: Adjust vector address with ol, (continued)
- [PATCH 07/13] target/riscv: Ajdust vector atomic check with ol, LIU Zhiwei, 2021/11/01
- [PATCH 06/13] target/riscv: Adjust vsetvl according to ol, LIU Zhiwei, 2021/11/01
- [PATCH 04/13] target/riscv: Use gdb xml according to max mxlen, LIU Zhiwei, 2021/11/01
- [PATCH 10/13] target/riscv: Adjust scalar reg in vector with ol, LIU Zhiwei, 2021/11/01
- [PATCH 13/13] target/riscv: Enable uxl field write,
LIU Zhiwei <=
- [PATCH 08/13] target/riscv: Fix check range for first fault only, LIU Zhiwei, 2021/11/01
- [PATCH 12/13] target/riscv: Don't save pc when exception return, LIU Zhiwei, 2021/11/01