Re: [PATCH 13/13] target/riscv: Enable uxl field write

qemu-devel

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [PATCH 13/13] target/riscv: Enable uxl field write

From:	Richard Henderson
Subject:	Re: [PATCH 13/13] target/riscv: Enable uxl field write
Date:	Mon, 1 Nov 2021 13:01:31 -0400
User-agent:	Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.13.0

On 11/1/21 6:01 AM, LIU Zhiwei wrote:

          mask |= MSTATUS_MPV | MSTATUS_GVA;
+        if ((val ^ mstatus) & MSTATUS64_UXL) {
+            mask |= MSTATUS64_UXL;
+        }


Why do you need the conditional here?
Why is this not just

    mask |= MSTATUS_MPV | MSTATUS_GVA | MSTATUS64_UXL;

 static bool trans_csrrw(DisasContext *ctx, arg_csrrw *a)
 {
-    TCGv src = get_gpr(ctx, a->rs1, EXT_NONE);
+    TCGv src = get_gpr(ctx, a->rs1, EXT_ZERO);


Hmm.  Not sure about this.

It looks like we should in fact change mask, just a few lines down, at which point theextension (or not) for the source would not matter. And likewise in trans_csrrwi.

r~

[Prev in Thread]

Current Thread

[Next in Thread]

[PATCH 07/13] target/riscv: Ajdust vector atomic check with ol, (continued)
- [PATCH 07/13] target/riscv: Ajdust vector atomic check with ol, LIU Zhiwei, 2021/11/01
  - Re: [PATCH 07/13] target/riscv: Ajdust vector atomic check with ol, Richard Henderson, 2021/11/01
- [PATCH 06/13] target/riscv: Adjust vsetvl according to ol, LIU Zhiwei, 2021/11/01
  - Re: [PATCH 06/13] target/riscv: Adjust vsetvl according to ol, Richard Henderson, 2021/11/01
- [PATCH 04/13] target/riscv: Use gdb xml according to max mxlen, LIU Zhiwei, 2021/11/01
  - Re: [PATCH 04/13] target/riscv: Use gdb xml according to max mxlen, Richard Henderson, 2021/11/01
- [PATCH 10/13] target/riscv: Adjust scalar reg in vector with ol, LIU Zhiwei, 2021/11/01
  - Re: [PATCH 10/13] target/riscv: Adjust scalar reg in vector with ol, Richard Henderson, 2021/11/01
    - Re: [PATCH 10/13] target/riscv: Adjust scalar reg in vector with ol, LIU Zhiwei, 2021/11/08
- [PATCH 13/13] target/riscv: Enable uxl field write, LIU Zhiwei, 2021/11/01
  - Re: [PATCH 13/13] target/riscv: Enable uxl field write, Richard Henderson <=
    - Re: [PATCH 13/13] target/riscv: Enable uxl field write, LIU Zhiwei, 2021/11/08
    - Re: [PATCH 13/13] target/riscv: Enable uxl field write, LIU Zhiwei, 2021/11/09
- [PATCH 08/13] target/riscv: Fix check range for first fault only, LIU Zhiwei, 2021/11/01
  - Re: [PATCH 08/13] target/riscv: Fix check range for first fault only, Richard Henderson, 2021/11/01
- [PATCH 12/13] target/riscv: Don't save pc when exception return, LIU Zhiwei, 2021/11/01
  - Re: [PATCH 12/13] target/riscv: Don't save pc when exception return, Richard Henderson, 2021/11/01

Prev by Date: Re: [PATCH v5 06/26] arm: qemu: Add a devicetree file for qemu_arm64
Next by Date: Re: [PATCH v6 13/66] linux-user/host/s390: Populate host_signal.h
Previous by thread: [PATCH 13/13] target/riscv: Enable uxl field write
Next by thread: Re: [PATCH 13/13] target/riscv: Enable uxl field write
Index(es):
- Date
- Thread