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[PATCH 07/13] target/riscv: Ajdust vector atomic check with ol
From: |
LIU Zhiwei |
Subject: |
[PATCH 07/13] target/riscv: Ajdust vector atomic check with ol |
Date: |
Mon, 1 Nov 2021 18:01:37 +0800 |
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
target/riscv/insn_trans/trans_rvv.c.inc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index 01da065710..ed042f7bb9 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -739,7 +739,7 @@ static bool amo_check(DisasContext *s, arg_rwdvm* a)
(!a->wd || vext_check_overlap_mask(s, a->rd, a->vm, false)) &&
vext_check_reg(s, a->rd, false) &&
vext_check_reg(s, a->rs2, false) &&
- ((1 << s->sew) <= sizeof(target_ulong)) &&
+ ((1 << s->sew) <= (get_olen(s) / 8)) &&
((1 << s->sew) >= 4));
}
--
2.25.1
- Re: [PATCH 05/13] target/riscv: Calculate address according to ol, (continued)
- [PATCH 09/13] target/riscv: Adjust vector address with ol, LIU Zhiwei, 2021/11/01
- Re: [PATCH 09/13] target/riscv: Adjust vector address with ol, Richard Henderson, 2021/11/01
- Re: [PATCH 09/13] target/riscv: Adjust vector address with ol, LIU Zhiwei, 2021/11/08
- Re: [PATCH 09/13] target/riscv: Adjust vector address with ol, Richard Henderson, 2021/11/09
- Re: [PATCH 09/13] target/riscv: Adjust vector address with ol, LIU Zhiwei, 2021/11/09
- Re: [PATCH 09/13] target/riscv: Adjust vector address with ol, Richard Henderson, 2021/11/09
- Re: [PATCH 09/13] target/riscv: Adjust vector address with ol, LIU Zhiwei, 2021/11/09
- Re: [PATCH 09/13] target/riscv: Adjust vector address with ol, LIU Zhiwei, 2021/11/09
- Re: [PATCH 09/13] target/riscv: Adjust vector address with ol, Richard Henderson, 2021/11/09
[PATCH 07/13] target/riscv: Ajdust vector atomic check with ol,
LIU Zhiwei <=
[PATCH 06/13] target/riscv: Adjust vsetvl according to ol, LIU Zhiwei, 2021/11/01
[PATCH 04/13] target/riscv: Use gdb xml according to max mxlen, LIU Zhiwei, 2021/11/01
[PATCH 10/13] target/riscv: Adjust scalar reg in vector with ol, LIU Zhiwei, 2021/11/01
[PATCH 13/13] target/riscv: Enable uxl field write, LIU Zhiwei, 2021/11/01