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[PULL 17/33] target/riscv: Use gen_arith for mulh and mulhu
From: |
Alistair Francis |
Subject: |
[PULL 17/33] target/riscv: Use gen_arith for mulh and mulhu |
Date: |
Wed, 1 Sep 2021 12:09:42 +1000 |
From: Richard Henderson <richard.henderson@linaro.org>
Split out gen_mulh and gen_mulhu and use the common helper.
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210823195529.560295-9-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/insn_trans/trans_rvm.c.inc | 40 +++++++++++--------------
1 file changed, 18 insertions(+), 22 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvm.c.inc
b/target/riscv/insn_trans/trans_rvm.c.inc
index 3d93b24c25..80552be7a3 100644
--- a/target/riscv/insn_trans/trans_rvm.c.inc
+++ b/target/riscv/insn_trans/trans_rvm.c.inc
@@ -25,20 +25,18 @@ static bool trans_mul(DisasContext *ctx, arg_mul *a)
return gen_arith(ctx, a, EXT_NONE, tcg_gen_mul_tl);
}
-static bool trans_mulh(DisasContext *ctx, arg_mulh *a)
+static void gen_mulh(TCGv ret, TCGv s1, TCGv s2)
{
- REQUIRE_EXT(ctx, RVM);
- TCGv source1 = tcg_temp_new();
- TCGv source2 = tcg_temp_new();
- gen_get_gpr(ctx, source1, a->rs1);
- gen_get_gpr(ctx, source2, a->rs2);
+ TCGv discard = tcg_temp_new();
- tcg_gen_muls2_tl(source2, source1, source1, source2);
+ tcg_gen_muls2_tl(discard, ret, s1, s2);
+ tcg_temp_free(discard);
+}
- gen_set_gpr(ctx, a->rd, source1);
- tcg_temp_free(source1);
- tcg_temp_free(source2);
- return true;
+static bool trans_mulh(DisasContext *ctx, arg_mulh *a)
+{
+ REQUIRE_EXT(ctx, RVM);
+ return gen_arith(ctx, a, EXT_NONE, gen_mulh);
}
static bool trans_mulhsu(DisasContext *ctx, arg_mulhsu *a)
@@ -47,20 +45,18 @@ static bool trans_mulhsu(DisasContext *ctx, arg_mulhsu *a)
return gen_arith(ctx, a, EXT_NONE, gen_mulhsu);
}
-static bool trans_mulhu(DisasContext *ctx, arg_mulhu *a)
+static void gen_mulhu(TCGv ret, TCGv s1, TCGv s2)
{
- REQUIRE_EXT(ctx, RVM);
- TCGv source1 = tcg_temp_new();
- TCGv source2 = tcg_temp_new();
- gen_get_gpr(ctx, source1, a->rs1);
- gen_get_gpr(ctx, source2, a->rs2);
+ TCGv discard = tcg_temp_new();
- tcg_gen_mulu2_tl(source2, source1, source1, source2);
+ tcg_gen_mulu2_tl(discard, ret, s1, s2);
+ tcg_temp_free(discard);
+}
- gen_set_gpr(ctx, a->rd, source1);
- tcg_temp_free(source1);
- tcg_temp_free(source2);
- return true;
+static bool trans_mulhu(DisasContext *ctx, arg_mulhu *a)
+{
+ REQUIRE_EXT(ctx, RVM);
+ return gen_arith(ctx, a, EXT_NONE, gen_mulhu);
}
static bool trans_div(DisasContext *ctx, arg_div *a)
--
2.31.1
- [PULL 07/33] hw/intc/sifive_clint: Fix muldiv64 overflow in sifive_clint_write_timecmp(), (continued)
- [PULL 07/33] hw/intc/sifive_clint: Fix muldiv64 overflow in sifive_clint_write_timecmp(), Alistair Francis, 2021/08/31
- [PULL 06/33] hw/riscv/virt.c: Assemble plic_hart_config string with g_strjoinv(), Alistair Francis, 2021/08/31
- [PULL 08/33] hw/core/register: Add more 64-bit utilities, Alistair Francis, 2021/08/31
- [PULL 09/33] hw/registerfields: Use 64-bit bitfield for FIELD_DP64, Alistair Francis, 2021/08/31
- [PULL 10/33] target/riscv: Use tcg_constant_*, Alistair Francis, 2021/08/31
- [PULL 11/33] tests/tcg/riscv64: Add test for division, Alistair Francis, 2021/08/31
- [PULL 12/33] target/riscv: Clean up division helpers, Alistair Francis, 2021/08/31
- [PULL 15/33] target/riscv: Add DisasExtend to gen_arith*, Alistair Francis, 2021/08/31
- [PULL 13/33] target/riscv: Add DisasContext to gen_get_gpr, gen_set_gpr, Alistair Francis, 2021/08/31
- [PULL 16/33] target/riscv: Remove gen_arith_div*, Alistair Francis, 2021/08/31
- [PULL 17/33] target/riscv: Use gen_arith for mulh and mulhu,
Alistair Francis <=
- [PULL 14/33] target/riscv: Introduce DisasExtend and new helpers, Alistair Francis, 2021/08/31
- [PULL 18/33] target/riscv: Move gen_* helpers for RVM, Alistair Francis, 2021/08/31
- [PULL 19/33] target/riscv: Move gen_* helpers for RVB, Alistair Francis, 2021/08/31
- [PULL 20/33] target/riscv: Add DisasExtend to gen_unary, Alistair Francis, 2021/08/31
- [PULL 21/33] target/riscv: Use DisasExtend in shift operations, Alistair Francis, 2021/08/31
- [PULL 23/33] target/riscv: Use get_gpr in branches, Alistair Francis, 2021/08/31
- [PULL 22/33] target/riscv: Use extracts for sraiw and srliw, Alistair Francis, 2021/08/31
- [PULL 25/33] target/riscv: Fix rmw_sip, rmw_vsip, rmw_hsip vs write-only operation, Alistair Francis, 2021/08/31
- [PULL 24/33] target/riscv: Use {get, dest}_gpr for integer load/store, Alistair Francis, 2021/08/31
- [PULL 26/33] target/riscv: Fix hgeie, hgeip, Alistair Francis, 2021/08/31