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[PULL 12/33] target/riscv: Clean up division helpers
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From: |
Alistair Francis |
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Subject: |
[PULL 12/33] target/riscv: Clean up division helpers |
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Date: |
Wed, 1 Sep 2021 12:09:37 +1000 |
From: Richard Henderson <richard.henderson@linaro.org>
Utilize the condition in the movcond more; this allows some of
the setcond that were feeding into movcond to be removed.
Do not write into source1 and source2. Re-name "condN" to "tempN"
and use the temporaries for more than holding conditions.
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210823195529.560295-4-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/translate.c | 174 ++++++++++++++++++++-------------------
1 file changed, 91 insertions(+), 83 deletions(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 20a55c92fb..147b9c2f68 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -213,106 +213,114 @@ static void gen_mulhsu(TCGv ret, TCGv arg1, TCGv arg2)
static void gen_div(TCGv ret, TCGv source1, TCGv source2)
{
- TCGv cond1, cond2, zeroreg, resultopt1;
+ TCGv temp1, temp2, zero, one, mone, min;
+
+ temp1 = tcg_temp_new();
+ temp2 = tcg_temp_new();
+ zero = tcg_constant_tl(0);
+ one = tcg_constant_tl(1);
+ mone = tcg_constant_tl(-1);
+ min = tcg_constant_tl(1ull << (TARGET_LONG_BITS - 1));
+
/*
- * Handle by altering args to tcg_gen_div to produce req'd results:
- * For overflow: want source1 in source1 and 1 in source2
- * For div by zero: want -1 in source1 and 1 in source2 -> -1 result
+ * If overflow, set temp2 to 1, else source2.
+ * This produces the required result of min.
*/
- cond1 = tcg_temp_new();
- cond2 = tcg_temp_new();
- zeroreg = tcg_constant_tl(0);
- resultopt1 = tcg_temp_new();
-
- tcg_gen_movi_tl(resultopt1, (target_ulong)-1);
- tcg_gen_setcondi_tl(TCG_COND_EQ, cond2, source2, (target_ulong)(~0L));
- tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source1,
- ((target_ulong)1) << (TARGET_LONG_BITS - 1));
- tcg_gen_and_tl(cond1, cond1, cond2); /* cond1 = overflow */
- tcg_gen_setcondi_tl(TCG_COND_EQ, cond2, source2, 0); /* cond2 = div 0 */
- /* if div by zero, set source1 to -1, otherwise don't change */
- tcg_gen_movcond_tl(TCG_COND_EQ, source1, cond2, zeroreg, source1,
- resultopt1);
- /* if overflow or div by zero, set source2 to 1, else don't change */
- tcg_gen_or_tl(cond1, cond1, cond2);
- tcg_gen_movi_tl(resultopt1, (target_ulong)1);
- tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond1, zeroreg, source2,
- resultopt1);
- tcg_gen_div_tl(ret, source1, source2);
-
- tcg_temp_free(cond1);
- tcg_temp_free(cond2);
- tcg_temp_free(resultopt1);
+ tcg_gen_setcond_tl(TCG_COND_EQ, temp1, source1, min);
+ tcg_gen_setcond_tl(TCG_COND_EQ, temp2, source2, mone);
+ tcg_gen_and_tl(temp1, temp1, temp2);
+ tcg_gen_movcond_tl(TCG_COND_NE, temp2, temp1, zero, one, source2);
+
+ /*
+ * If div by zero, set temp1 to -1 and temp2 to 1 to
+ * produce the required result of -1.
+ */
+ tcg_gen_movcond_tl(TCG_COND_EQ, temp1, source2, zero, mone, source1);
+ tcg_gen_movcond_tl(TCG_COND_EQ, temp2, source2, zero, one, temp2);
+
+ tcg_gen_div_tl(ret, temp1, temp2);
+
+ tcg_temp_free(temp1);
+ tcg_temp_free(temp2);
}
static void gen_divu(TCGv ret, TCGv source1, TCGv source2)
{
- TCGv cond1, zeroreg, resultopt1;
- cond1 = tcg_temp_new();
+ TCGv temp1, temp2, zero, one, max;
- zeroreg = tcg_constant_tl(0);
- resultopt1 = tcg_temp_new();
+ temp1 = tcg_temp_new();
+ temp2 = tcg_temp_new();
+ zero = tcg_constant_tl(0);
+ one = tcg_constant_tl(1);
+ max = tcg_constant_tl(~0);
- tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source2, 0);
- tcg_gen_movi_tl(resultopt1, (target_ulong)-1);
- tcg_gen_movcond_tl(TCG_COND_EQ, source1, cond1, zeroreg, source1,
- resultopt1);
- tcg_gen_movi_tl(resultopt1, (target_ulong)1);
- tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond1, zeroreg, source2,
- resultopt1);
- tcg_gen_divu_tl(ret, source1, source2);
+ /*
+ * If div by zero, set temp1 to max and temp2 to 1 to
+ * produce the required result of max.
+ */
+ tcg_gen_movcond_tl(TCG_COND_EQ, temp1, source2, zero, max, source1);
+ tcg_gen_movcond_tl(TCG_COND_EQ, temp2, source2, zero, one, source2);
+ tcg_gen_divu_tl(ret, temp1, temp2);
- tcg_temp_free(cond1);
- tcg_temp_free(resultopt1);
+ tcg_temp_free(temp1);
+ tcg_temp_free(temp2);
}
static void gen_rem(TCGv ret, TCGv source1, TCGv source2)
{
- TCGv cond1, cond2, zeroreg, resultopt1;
-
- cond1 = tcg_temp_new();
- cond2 = tcg_temp_new();
- zeroreg = tcg_constant_tl(0);
- resultopt1 = tcg_temp_new();
-
- tcg_gen_movi_tl(resultopt1, 1L);
- tcg_gen_setcondi_tl(TCG_COND_EQ, cond2, source2, (target_ulong)-1);
- tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source1,
- (target_ulong)1 << (TARGET_LONG_BITS - 1));
- tcg_gen_and_tl(cond2, cond1, cond2); /* cond1 = overflow */
- tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source2, 0); /* cond2 = div 0 */
- /* if overflow or div by zero, set source2 to 1, else don't change */
- tcg_gen_or_tl(cond2, cond1, cond2);
- tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond2, zeroreg, source2,
- resultopt1);
- tcg_gen_rem_tl(resultopt1, source1, source2);
- /* if div by zero, just return the original dividend */
- tcg_gen_movcond_tl(TCG_COND_EQ, ret, cond1, zeroreg, resultopt1,
- source1);
-
- tcg_temp_free(cond1);
- tcg_temp_free(cond2);
- tcg_temp_free(resultopt1);
+ TCGv temp1, temp2, zero, one, mone, min;
+
+ temp1 = tcg_temp_new();
+ temp2 = tcg_temp_new();
+ zero = tcg_constant_tl(0);
+ one = tcg_constant_tl(1);
+ mone = tcg_constant_tl(-1);
+ min = tcg_constant_tl(1ull << (TARGET_LONG_BITS - 1));
+
+ /*
+ * If overflow, set temp1 to 0, else source1.
+ * This avoids a possible host trap, and produces the required result of 0.
+ */
+ tcg_gen_setcond_tl(TCG_COND_EQ, temp1, source1, min);
+ tcg_gen_setcond_tl(TCG_COND_EQ, temp2, source2, mone);
+ tcg_gen_and_tl(temp1, temp1, temp2);
+ tcg_gen_movcond_tl(TCG_COND_NE, temp1, temp1, zero, zero, source1);
+
+ /*
+ * If div by zero, set temp2 to 1, else source2.
+ * This avoids a possible host trap, but produces an incorrect result.
+ */
+ tcg_gen_movcond_tl(TCG_COND_EQ, temp2, source2, zero, one, source2);
+
+ tcg_gen_rem_tl(temp1, temp1, temp2);
+
+ /* If div by zero, the required result is the original dividend. */
+ tcg_gen_movcond_tl(TCG_COND_EQ, ret, source2, zero, source1, temp1);
+
+ tcg_temp_free(temp1);
+ tcg_temp_free(temp2);
}
static void gen_remu(TCGv ret, TCGv source1, TCGv source2)
{
- TCGv cond1, zeroreg, resultopt1;
- cond1 = tcg_temp_new();
- zeroreg = tcg_constant_tl(0);
- resultopt1 = tcg_temp_new();
-
- tcg_gen_movi_tl(resultopt1, (target_ulong)1);
- tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source2, 0);
- tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond1, zeroreg, source2,
- resultopt1);
- tcg_gen_remu_tl(resultopt1, source1, source2);
- /* if div by zero, just return the original dividend */
- tcg_gen_movcond_tl(TCG_COND_EQ, ret, cond1, zeroreg, resultopt1,
- source1);
-
- tcg_temp_free(cond1);
- tcg_temp_free(resultopt1);
+ TCGv temp, zero, one;
+
+ temp = tcg_temp_new();
+ zero = tcg_constant_tl(0);
+ one = tcg_constant_tl(1);
+
+ /*
+ * If div by zero, set temp to 1, else source2.
+ * This avoids a possible host trap, but produces an incorrect result.
+ */
+ tcg_gen_movcond_tl(TCG_COND_EQ, temp, source2, zero, one, source2);
+
+ tcg_gen_remu_tl(temp, source1, temp);
+
+ /* If div by zero, the required result is the original dividend. */
+ tcg_gen_movcond_tl(TCG_COND_EQ, ret, source2, zero, source1, temp);
+
+ tcg_temp_free(temp);
}
static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
--
2.31.1
- [PULL 02/33] hw/riscv: virt: Move flash node to root, (continued)
- [PULL 02/33] hw/riscv: virt: Move flash node to root, Alistair Francis, 2021/08/31
- [PULL 03/33] target/riscv: Correct a comment in riscv_csrrw(), Alistair Francis, 2021/08/31
- [PULL 04/33] target/riscv: Don't wrongly override isa version, Alistair Francis, 2021/08/31
- [PULL 05/33] target/riscv: Add User CSRs read-only check, Alistair Francis, 2021/08/31
- [PULL 07/33] hw/intc/sifive_clint: Fix muldiv64 overflow in sifive_clint_write_timecmp(), Alistair Francis, 2021/08/31
- [PULL 06/33] hw/riscv/virt.c: Assemble plic_hart_config string with g_strjoinv(), Alistair Francis, 2021/08/31
- [PULL 08/33] hw/core/register: Add more 64-bit utilities, Alistair Francis, 2021/08/31
- [PULL 09/33] hw/registerfields: Use 64-bit bitfield for FIELD_DP64, Alistair Francis, 2021/08/31
- [PULL 10/33] target/riscv: Use tcg_constant_*, Alistair Francis, 2021/08/31
- [PULL 11/33] tests/tcg/riscv64: Add test for division, Alistair Francis, 2021/08/31
- [PULL 12/33] target/riscv: Clean up division helpers,
Alistair Francis <=
- [PULL 15/33] target/riscv: Add DisasExtend to gen_arith*, Alistair Francis, 2021/08/31
- [PULL 13/33] target/riscv: Add DisasContext to gen_get_gpr, gen_set_gpr, Alistair Francis, 2021/08/31
- [PULL 16/33] target/riscv: Remove gen_arith_div*, Alistair Francis, 2021/08/31
- [PULL 17/33] target/riscv: Use gen_arith for mulh and mulhu, Alistair Francis, 2021/08/31
- [PULL 14/33] target/riscv: Introduce DisasExtend and new helpers, Alistair Francis, 2021/08/31
- [PULL 18/33] target/riscv: Move gen_* helpers for RVM, Alistair Francis, 2021/08/31
- [PULL 19/33] target/riscv: Move gen_* helpers for RVB, Alistair Francis, 2021/08/31
- [PULL 20/33] target/riscv: Add DisasExtend to gen_unary, Alistair Francis, 2021/08/31
- [PULL 21/33] target/riscv: Use DisasExtend in shift operations, Alistair Francis, 2021/08/31
- [PULL 23/33] target/riscv: Use get_gpr in branches, Alistair Francis, 2021/08/31