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[PULL 08/33] hw/core/register: Add more 64-bit utilities
From: |
Alistair Francis |
Subject: |
[PULL 08/33] hw/core/register: Add more 64-bit utilities |
Date: |
Wed, 1 Sep 2021 12:09:33 +1000 |
From: Joe Komlodi <joe.komlodi@xilinx.com>
We already have some utilities to handle 64-bit wide registers, so this just
adds some more for:
- Initializing 64-bit registers
- Extracting and depositing to an array of 64-bit registers
Signed-off-by: Joe Komlodi <joe.komlodi@xilinx.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1626805903-162860-2-git-send-email-joe.komlodi@xilinx.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
include/hw/register.h | 8 ++++++++
include/hw/registerfields.h | 8 ++++++++
hw/core/register.c | 12 ++++++++++++
3 files changed, 28 insertions(+)
diff --git a/include/hw/register.h b/include/hw/register.h
index b480e3882c..6a076cfcdf 100644
--- a/include/hw/register.h
+++ b/include/hw/register.h
@@ -204,6 +204,14 @@ RegisterInfoArray *register_init_block32(DeviceState
*owner,
bool debug_enabled,
uint64_t memory_size);
+RegisterInfoArray *register_init_block64(DeviceState *owner,
+ const RegisterAccessInfo *rae,
+ int num, RegisterInfo *ri,
+ uint64_t *data,
+ const MemoryRegionOps *ops,
+ bool debug_enabled,
+ uint64_t memory_size);
+
/**
* This function should be called to cleanup the registers that were
initialized
* when calling register_init_block32(). This function should only be called
diff --git a/include/hw/registerfields.h b/include/hw/registerfields.h
index 93fa4a84c2..9a03ac55e4 100644
--- a/include/hw/registerfields.h
+++ b/include/hw/registerfields.h
@@ -30,6 +30,10 @@
enum { A_ ## reg = (addr) }; \
enum { R_ ## reg = (addr) / 2 };
+#define REG64(reg, addr) \
+ enum { A_ ## reg = (addr) }; \
+ enum { R_ ## reg = (addr) / 8 };
+
/* Define SHIFT, LENGTH and MASK constants for a field within a register */
/* This macro will define R_FOO_BAR_MASK, R_FOO_BAR_SHIFT and R_FOO_BAR_LENGTH
@@ -58,6 +62,8 @@
/* Extract a field from an array of registers */
#define ARRAY_FIELD_EX32(regs, reg, field) \
FIELD_EX32((regs)[R_ ## reg], reg, field)
+#define ARRAY_FIELD_EX64(regs, reg, field) \
+ FIELD_EX64((regs)[R_ ## reg], reg, field)
/* Deposit a register field.
* Assigning values larger then the target field will result in
@@ -99,5 +105,7 @@
/* Deposit a field to array of registers. */
#define ARRAY_FIELD_DP32(regs, reg, field, val) \
(regs)[R_ ## reg] = FIELD_DP32((regs)[R_ ## reg], reg, field, val);
+#define ARRAY_FIELD_DP64(regs, reg, field, val) \
+ (regs)[R_ ## reg] = FIELD_DP64((regs)[R_ ## reg], reg, field, val);
#endif
diff --git a/hw/core/register.c b/hw/core/register.c
index d6f8c20816..95b0150c0a 100644
--- a/hw/core/register.c
+++ b/hw/core/register.c
@@ -300,6 +300,18 @@ RegisterInfoArray *register_init_block32(DeviceState
*owner,
data, ops, debug_enabled, memory_size, 32);
}
+RegisterInfoArray *register_init_block64(DeviceState *owner,
+ const RegisterAccessInfo *rae,
+ int num, RegisterInfo *ri,
+ uint64_t *data,
+ const MemoryRegionOps *ops,
+ bool debug_enabled,
+ uint64_t memory_size)
+{
+ return register_init_block(owner, rae, num, ri, (void *)
+ data, ops, debug_enabled, memory_size, 64);
+}
+
void register_finalize_block(RegisterInfoArray *r_array)
{
object_unparent(OBJECT(&r_array->mem));
--
2.31.1
- [PULL 00/33] riscv-to-apply queue, Alistair Francis, 2021/08/31
- [PULL 01/33] hw/char: Add config for shakti uart, Alistair Francis, 2021/08/31
- [PULL 02/33] hw/riscv: virt: Move flash node to root, Alistair Francis, 2021/08/31
- [PULL 03/33] target/riscv: Correct a comment in riscv_csrrw(), Alistair Francis, 2021/08/31
- [PULL 04/33] target/riscv: Don't wrongly override isa version, Alistair Francis, 2021/08/31
- [PULL 05/33] target/riscv: Add User CSRs read-only check, Alistair Francis, 2021/08/31
- [PULL 07/33] hw/intc/sifive_clint: Fix muldiv64 overflow in sifive_clint_write_timecmp(), Alistair Francis, 2021/08/31
- [PULL 06/33] hw/riscv/virt.c: Assemble plic_hart_config string with g_strjoinv(), Alistair Francis, 2021/08/31
- [PULL 08/33] hw/core/register: Add more 64-bit utilities,
Alistair Francis <=
- [PULL 09/33] hw/registerfields: Use 64-bit bitfield for FIELD_DP64, Alistair Francis, 2021/08/31
- [PULL 10/33] target/riscv: Use tcg_constant_*, Alistair Francis, 2021/08/31
- [PULL 11/33] tests/tcg/riscv64: Add test for division, Alistair Francis, 2021/08/31
- [PULL 12/33] target/riscv: Clean up division helpers, Alistair Francis, 2021/08/31
- [PULL 15/33] target/riscv: Add DisasExtend to gen_arith*, Alistair Francis, 2021/08/31
- [PULL 13/33] target/riscv: Add DisasContext to gen_get_gpr, gen_set_gpr, Alistair Francis, 2021/08/31
- [PULL 16/33] target/riscv: Remove gen_arith_div*, Alistair Francis, 2021/08/31
- [PULL 17/33] target/riscv: Use gen_arith for mulh and mulhu, Alistair Francis, 2021/08/31
- [PULL 14/33] target/riscv: Introduce DisasExtend and new helpers, Alistair Francis, 2021/08/31
- [PULL 18/33] target/riscv: Move gen_* helpers for RVM, Alistair Francis, 2021/08/31