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[PULL 11/28] target/mips: Convert Vr54xx MUL* opcodes to decodetree
From: |
Philippe Mathieu-Daudé |
Subject: |
[PULL 11/28] target/mips: Convert Vr54xx MUL* opcodes to decodetree |
Date: |
Wed, 25 Aug 2021 15:01:54 +0200 |
Convert the following Integer Multiply-Accumulate opcodes:
* MULHI Multiply and move HI
* MULHIU Unsigned multiply and move HI
* MULS Multiply, negate, and move LO
* MULSHI Multiply, negate, and move HI
* MULSHIU Unsigned multiply, negate, and move HI
* MULSU Unsigned multiply, negate, and move LO
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210808173018.90960-7-f4bug@amsat.org>
---
target/mips/tcg/vr54xx.decode | 6 ++++++
target/mips/tcg/translate.c | 24 ------------------------
target/mips/tcg/vr54xx_translate.c | 12 ++++++++++++
3 files changed, 18 insertions(+), 24 deletions(-)
diff --git a/target/mips/tcg/vr54xx.decode b/target/mips/tcg/vr54xx.decode
index 73778f101a5..79bb5175eab 100644
--- a/target/mips/tcg/vr54xx.decode
+++ b/target/mips/tcg/vr54xx.decode
@@ -11,7 +11,13 @@
@rs_rt_rd ...... rs:5 rt:5 rd:5 ..... ...... &r
+MULS 000000 ..... ..... ..... 00011011000 @rs_rt_rd
+MULSU 000000 ..... ..... ..... 00011011001 @rs_rt_rd
MACC 000000 ..... ..... ..... 00101011000 @rs_rt_rd
MACCU 000000 ..... ..... ..... 00101011001 @rs_rt_rd
+MULHI 000000 ..... ..... ..... 01001011000 @rs_rt_rd
+MULHIU 000000 ..... ..... ..... 01001011001 @rs_rt_rd
+MULSHI 000000 ..... ..... ..... 01011011000 @rs_rt_rd
+MULSHIU 000000 ..... ..... ..... 01011011001 @rs_rt_rd
MACCHI 000000 ..... ..... ..... 01101011000 @rs_rt_rd
MACCHIU 000000 ..... ..... ..... 01101011001 @rs_rt_rd
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index fd8ffadf06e..4b7f2d9ae8b 100644
--- a/target/mips/tcg/translate.c
+++ b/target/mips/tcg/translate.c
@@ -298,14 +298,8 @@ enum {
#define MASK_MUL_VR54XX(op) (MASK_SPECIAL(op) | (op & (0x1F << 6)))
enum {
- OPC_VR54XX_MULS = (0x03 << 6) | OPC_MULT,
- OPC_VR54XX_MULSU = (0x03 << 6) | OPC_MULTU,
OPC_VR54XX_MSAC = (0x07 << 6) | OPC_MULT,
OPC_VR54XX_MSACU = (0x07 << 6) | OPC_MULTU,
- OPC_VR54XX_MULHI = (0x09 << 6) | OPC_MULT,
- OPC_VR54XX_MULHIU = (0x09 << 6) | OPC_MULTU,
- OPC_VR54XX_MULSHI = (0x0B << 6) | OPC_MULT,
- OPC_VR54XX_MULSHIU = (0x0B << 6) | OPC_MULTU,
OPC_VR54XX_MSACHI = (0x0F << 6) | OPC_MULT,
OPC_VR54XX_MSACHIU = (0x0F << 6) | OPC_MULTU,
};
@@ -3770,30 +3764,12 @@ static void gen_mul_vr54xx(DisasContext *ctx, uint32_t
opc,
gen_load_gpr(t1, rt);
switch (opc) {
- case OPC_VR54XX_MULS:
- gen_helper_muls(t0, cpu_env, t0, t1);
- break;
- case OPC_VR54XX_MULSU:
- gen_helper_mulsu(t0, cpu_env, t0, t1);
- break;
case OPC_VR54XX_MSAC:
gen_helper_msac(t0, cpu_env, t0, t1);
break;
case OPC_VR54XX_MSACU:
gen_helper_msacu(t0, cpu_env, t0, t1);
break;
- case OPC_VR54XX_MULHI:
- gen_helper_mulhi(t0, cpu_env, t0, t1);
- break;
- case OPC_VR54XX_MULHIU:
- gen_helper_mulhiu(t0, cpu_env, t0, t1);
- break;
- case OPC_VR54XX_MULSHI:
- gen_helper_mulshi(t0, cpu_env, t0, t1);
- break;
- case OPC_VR54XX_MULSHIU:
- gen_helper_mulshiu(t0, cpu_env, t0, t1);
- break;
case OPC_VR54XX_MSACHI:
gen_helper_msachi(t0, cpu_env, t0, t1);
break;
diff --git a/target/mips/tcg/vr54xx_translate.c
b/target/mips/tcg/vr54xx_translate.c
index 0e2d460c985..9f35b2c7e5d 100644
--- a/target/mips/tcg/vr54xx_translate.c
+++ b/target/mips/tcg/vr54xx_translate.c
@@ -25,6 +25,12 @@
* MACCHI Multiply, accumulate, and move HI
* MACCHIU Unsigned multiply, accumulate, and move HI
* MACCU Unsigned multiply, accumulate, and move LO
+ * MULHI Multiply and move HI
+ * MULHIU Unsigned multiply and move HI
+ * MULS Multiply, negate, and move LO
+ * MULSHI Multiply, negate, and move HI
+ * MULSHIU Unsigned multiply, negate, and move HI
+ * MULSU Unsigned multiply, negate, and move LO
*/
static bool trans_mult_acc(DisasContext *ctx, arg_r *a,
@@ -50,3 +56,9 @@ TRANS(MACC, trans_mult_acc, gen_helper_macc);
TRANS(MACCHI, trans_mult_acc, gen_helper_macchi);
TRANS(MACCHIU, trans_mult_acc, gen_helper_macchiu);
TRANS(MACCU, trans_mult_acc, gen_helper_maccu);
+TRANS(MULHI, trans_mult_acc, gen_helper_mulhi);
+TRANS(MULHIU, trans_mult_acc, gen_helper_mulhiu);
+TRANS(MULS, trans_mult_acc, gen_helper_muls);
+TRANS(MULSHI, trans_mult_acc, gen_helper_mulshi);
+TRANS(MULSHIU, trans_mult_acc, gen_helper_mulshiu);
+TRANS(MULSU, trans_mult_acc, gen_helper_mulsu);
--
2.31.1
- [PULL 01/28] target/mips: Remove JR opcode unused arguments, (continued)
- [PULL 01/28] target/mips: Remove JR opcode unused arguments, Philippe Mathieu-Daudé, 2021/08/25
- [PULL 02/28] target/mips: Simplify PREF opcode, Philippe Mathieu-Daudé, 2021/08/25
- [PULL 03/28] target/mips: Decode vendor extensions before MIPS ISAs, Philippe Mathieu-Daudé, 2021/08/25
- [PULL 04/28] target/mips: Merge 32-bit/64-bit Release6 decodetree definitions, Philippe Mathieu-Daudé, 2021/08/25
- [PULL 06/28] target/mips: Introduce generic TRANS() macro for decodetree helpers, Philippe Mathieu-Daudé, 2021/08/25
- [PULL 05/28] target/mips: Rename 'rtype' as 'r', Philippe Mathieu-Daudé, 2021/08/25
- [PULL 07/28] target/mips: Extract NEC Vr54xx helper definitions, Philippe Mathieu-Daudé, 2021/08/25
- [PULL 08/28] target/mips: Extract NEC Vr54xx helpers to vr54xx_helper.c, Philippe Mathieu-Daudé, 2021/08/25
- [PULL 09/28] target/mips: Introduce decodetree structure for NEC Vr54xx extension, Philippe Mathieu-Daudé, 2021/08/25
- [PULL 10/28] target/mips: Convert Vr54xx MACC* opcodes to decodetree, Philippe Mathieu-Daudé, 2021/08/25
- [PULL 11/28] target/mips: Convert Vr54xx MUL* opcodes to decodetree,
Philippe Mathieu-Daudé <=
- [PULL 12/28] target/mips: Convert Vr54xx MSA* opcodes to decodetree, Philippe Mathieu-Daudé, 2021/08/25
- [PULL 13/28] target/mips: Document Loongson-3A CPU definitions, Philippe Mathieu-Daudé, 2021/08/25
- [PULL 14/28] target/mips: Allow Loongson 3A1000 to use up to 48-bit VAddr, Philippe Mathieu-Daudé, 2021/08/25
- [PULL 15/28] target/mips: Remove duplicated check_cp1_enabled() calls in Loongson EXT, Philippe Mathieu-Daudé, 2021/08/25
- [PULL 16/28] target/mips: Remove gen_helper_0e3i(), Philippe Mathieu-Daudé, 2021/08/25
- [PULL 17/28] target/mips: Remove gen_helper_1e2i(), Philippe Mathieu-Daudé, 2021/08/25
- [PULL 18/28] target/mips: Use tcg_constant_i32() in gen_helper_0e2i(), Philippe Mathieu-Daudé, 2021/08/25
- [PULL 19/28] target/mips: Simplify gen_helper() macros by using tcg_constant_i32(), Philippe Mathieu-Daudé, 2021/08/25
- [PULL 20/28] target/mips: Inline gen_helper_1e1i() call in op_ld_INSN() macros, Philippe Mathieu-Daudé, 2021/08/25
- [PULL 21/28] target/mips: Inline gen_helper_0e0i(), Philippe Mathieu-Daudé, 2021/08/25