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[PULL 21/28] target/mips: Inline gen_helper_0e0i()
From: |
Philippe Mathieu-Daudé |
Subject: |
[PULL 21/28] target/mips: Inline gen_helper_0e0i() |
Date: |
Wed, 25 Aug 2021 15:02:04 +0200 |
gen_helper_0e0i() is one-line long and is only used twice:
simply inline it.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210816205107.2051495-7-f4bug@amsat.org>
---
target/mips/tcg/translate.c | 8 ++------
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index db7fc75d937..c515a337ebc 100644
--- a/target/mips/tcg/translate.c
+++ b/target/mips/tcg/translate.c
@@ -1213,10 +1213,6 @@ TCGv_i64 fpu_f64[32];
#include "exec/gen-icount.h"
-#define gen_helper_0e0i(name, arg) do { \
- gen_helper_##name(cpu_env, tcg_constant_i32(arg)); \
- } while (0)
-
#define gen_helper_0e1i(name, arg1, arg2) do { \
gen_helper_##name(cpu_env, arg1, tcg_constant_i32(arg2)); \
} while (0)
@@ -1378,7 +1374,7 @@ void generate_exception_err(DisasContext *ctx, int excp,
int err)
void generate_exception(DisasContext *ctx, int excp)
{
- gen_helper_0e0i(raise_exception, excp);
+ gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp));
}
void generate_exception_end(DisasContext *ctx, int excp)
@@ -14188,7 +14184,7 @@ static void decode_opc_special(CPUMIPSState *env,
DisasContext *ctx)
MIPS_INVAL("PMON / selsl");
gen_reserved_instruction(ctx);
#else
- gen_helper_0e0i(pmon, sa);
+ gen_helper_pmon(cpu_env, tcg_constant_i32(sa));
#endif
break;
case OPC_SYSCALL:
--
2.31.1
- [PULL 11/28] target/mips: Convert Vr54xx MUL* opcodes to decodetree, (continued)
- [PULL 11/28] target/mips: Convert Vr54xx MUL* opcodes to decodetree, Philippe Mathieu-Daudé, 2021/08/25
- [PULL 12/28] target/mips: Convert Vr54xx MSA* opcodes to decodetree, Philippe Mathieu-Daudé, 2021/08/25
- [PULL 13/28] target/mips: Document Loongson-3A CPU definitions, Philippe Mathieu-Daudé, 2021/08/25
- [PULL 14/28] target/mips: Allow Loongson 3A1000 to use up to 48-bit VAddr, Philippe Mathieu-Daudé, 2021/08/25
- [PULL 15/28] target/mips: Remove duplicated check_cp1_enabled() calls in Loongson EXT, Philippe Mathieu-Daudé, 2021/08/25
- [PULL 16/28] target/mips: Remove gen_helper_0e3i(), Philippe Mathieu-Daudé, 2021/08/25
- [PULL 17/28] target/mips: Remove gen_helper_1e2i(), Philippe Mathieu-Daudé, 2021/08/25
- [PULL 18/28] target/mips: Use tcg_constant_i32() in gen_helper_0e2i(), Philippe Mathieu-Daudé, 2021/08/25
- [PULL 19/28] target/mips: Simplify gen_helper() macros by using tcg_constant_i32(), Philippe Mathieu-Daudé, 2021/08/25
- [PULL 20/28] target/mips: Inline gen_helper_1e1i() call in op_ld_INSN() macros, Philippe Mathieu-Daudé, 2021/08/25
- [PULL 21/28] target/mips: Inline gen_helper_0e0i(),
Philippe Mathieu-Daudé <=
- [PULL 22/28] target/mips: Use tcg_constant_i32() in generate_exception_err(), Philippe Mathieu-Daudé, 2021/08/25
- [PULL 23/28] target/mips: Define gen_helper() macros in translate.h, Philippe Mathieu-Daudé, 2021/08/25
- [PULL 24/28] target/mips: Call cpu_is_bigendian & inline GET_OFFSET in ld/st helpers, Philippe Mathieu-Daudé, 2021/08/25
- [PULL 25/28] target/mips: Replace GET_LMASK() macro by get_lmask(32) function, Philippe Mathieu-Daudé, 2021/08/25
- [PULL 26/28] target/mips: Replace GET_LMASK64() macro by get_lmask(64) function, Philippe Mathieu-Daudé, 2021/08/25
- [PULL 27/28] target/mips: Store CP0_Config0 in DisasContext, Philippe Mathieu-Daudé, 2021/08/25
- [PULL 28/28] target/mips: Replace TARGET_WORDS_BIGENDIAN by cpu_is_bigendian(), Philippe Mathieu-Daudé, 2021/08/25
- Re: [PULL 00/28] MIPS patches for 2021-08-25, Peter Maydell, 2021/08/26