[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [PATCH v3 13/14] tcg/arm: Reserve a register for guest_base
From: |
Peter Maydell |
Subject: |
Re: [PATCH v3 13/14] tcg/arm: Reserve a register for guest_base |
Date: |
Fri, 20 Aug 2021 13:03:15 +0100 |
On Wed, 18 Aug 2021 at 22:33, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Reserve a register for the guest_base using aarch64 for reference.
> By doing so, we do not have to recompute it for every memory load.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> tcg/arm/tcg-target.c.inc | 39 ++++++++++++++++++++++++++++-----------
> 1 file changed, 28 insertions(+), 11 deletions(-)
>
> diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
> index 35bd4c68d6..2728035177 100644
> --- a/tcg/arm/tcg-target.c.inc
> +++ b/tcg/arm/tcg-target.c.inc
> @@ -84,6 +84,9 @@ static const int tcg_target_call_oarg_regs[2] = {
>
> #define TCG_REG_TMP TCG_REG_R12
> #define TCG_VEC_TMP TCG_REG_Q15
> +#ifndef CONFIG_SOFTMMU
> +#define TCG_REG_GUEST_BASE TCG_REG_R11
> +#endif
>
> typedef enum {
> COND_EQ = 0x0,
> @@ -1763,7 +1766,8 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s,
> TCGLabelQemuLdst *lb)
>
> static void tcg_out_qemu_ld_index(TCGContext *s, MemOp opc,
> TCGReg datalo, TCGReg datahi,
> - TCGReg addrlo, TCGReg addend)
> + TCGReg addrlo, TCGReg addend,
> + bool scratch_addend)
> {
> /* Byte swapping is left to middle-end expansion. */
> tcg_debug_assert((opc & MO_BSWAP) == 0);
> @@ -1790,7 +1794,7 @@ static void tcg_out_qemu_ld_index(TCGContext *s, MemOp
> opc,
> && get_alignment_bits(opc) >= MO_64
> && (datalo & 1) == 0 && datahi == datalo + 1) {
> tcg_out_ldrd_r(s, COND_AL, datalo, addrlo, addend);
> - } else if (datalo != addend) {
> + } else if (scratch_addend) {
> tcg_out_ld32_rwb(s, COND_AL, datalo, addend, addrlo);
> tcg_out_ld32_12(s, COND_AL, datahi, addend, 4);
> } else {
I don't understand this change. Yes, we can trash the addend
register, but if it's the same as 'datalo' then the second load
is not going to DTRT... Shouldn't this be
if (scratch_addend && datalo != addend)
?
-- PMM
- [PATCH v3 02/14] tcg/arm: Standardize on tcg_out_<branch>_{reg,imm}, (continued)
- [PATCH v3 02/14] tcg/arm: Standardize on tcg_out_<branch>_{reg,imm}, Richard Henderson, 2021/08/18
- [PATCH v3 08/14] tcg/arm: Simplify usage of encode_imm, Richard Henderson, 2021/08/18
- [PATCH v3 09/14] tcg/arm: Drop inline markers, Richard Henderson, 2021/08/18
- [PATCH v3 10/14] tcg/arm: Give enum arm_cond_code_e a typedef and use it, Richard Henderson, 2021/08/18
- [PATCH v3 13/14] tcg/arm: Reserve a register for guest_base, Richard Henderson, 2021/08/18
- Re: [PATCH v3 13/14] tcg/arm: Reserve a register for guest_base,
Peter Maydell <=
- [PATCH v3 12/14] tcg/arm: More use of the TCGReg enum, Richard Henderson, 2021/08/18
- [PATCH v3 11/14] tcg/arm: More use of the ARMInsn enum, Richard Henderson, 2021/08/18
- [PATCH v3 14/14] tcg/arm: Support raising sigbus for user-only, Richard Henderson, 2021/08/18