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[PULL 09/11] char: ibex_uart: Update the register layout
From: |
Alistair Francis |
Subject: |
[PULL 09/11] char: ibex_uart: Update the register layout |
Date: |
Mon, 12 Jul 2021 15:53:46 -0700 |
Update the register layout to match the latest OpenTitan bitstream.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id:
25c8377d32f3e0f0a1a862c8a5092f8a9e3f9928.1625801868.git.alistair.francis@wdc.com
---
hw/char/ibex_uart.c | 19 ++++++++++---------
1 file changed, 10 insertions(+), 9 deletions(-)
diff --git a/hw/char/ibex_uart.c b/hw/char/ibex_uart.c
index fe4b6c3c9e..6b0c9330bf 100644
--- a/hw/char/ibex_uart.c
+++ b/hw/char/ibex_uart.c
@@ -42,7 +42,8 @@ REG32(INTR_STATE, 0x00)
FIELD(INTR_STATE, RX_OVERFLOW, 3, 1)
REG32(INTR_ENABLE, 0x04)
REG32(INTR_TEST, 0x08)
-REG32(CTRL, 0x0C)
+REG32(ALERT_TEST, 0x0C)
+REG32(CTRL, 0x10)
FIELD(CTRL, TX_ENABLE, 0, 1)
FIELD(CTRL, RX_ENABLE, 1, 1)
FIELD(CTRL, NF, 2, 1)
@@ -52,25 +53,25 @@ REG32(CTRL, 0x0C)
FIELD(CTRL, PARITY_ODD, 7, 1)
FIELD(CTRL, RXBLVL, 8, 2)
FIELD(CTRL, NCO, 16, 16)
-REG32(STATUS, 0x10)
+REG32(STATUS, 0x14)
FIELD(STATUS, TXFULL, 0, 1)
FIELD(STATUS, RXFULL, 1, 1)
FIELD(STATUS, TXEMPTY, 2, 1)
FIELD(STATUS, RXIDLE, 4, 1)
FIELD(STATUS, RXEMPTY, 5, 1)
-REG32(RDATA, 0x14)
-REG32(WDATA, 0x18)
-REG32(FIFO_CTRL, 0x1c)
+REG32(RDATA, 0x18)
+REG32(WDATA, 0x1C)
+REG32(FIFO_CTRL, 0x20)
FIELD(FIFO_CTRL, RXRST, 0, 1)
FIELD(FIFO_CTRL, TXRST, 1, 1)
FIELD(FIFO_CTRL, RXILVL, 2, 3)
FIELD(FIFO_CTRL, TXILVL, 5, 2)
-REG32(FIFO_STATUS, 0x20)
+REG32(FIFO_STATUS, 0x24)
FIELD(FIFO_STATUS, TXLVL, 0, 5)
FIELD(FIFO_STATUS, RXLVL, 16, 5)
-REG32(OVRD, 0x24)
-REG32(VAL, 0x28)
-REG32(TIMEOUT_CTRL, 0x2c)
+REG32(OVRD, 0x28)
+REG32(VAL, 0x2C)
+REG32(TIMEOUT_CTRL, 0x30)
static void ibex_uart_update_irqs(IbexUartState *s)
{
--
2.31.1
- [PULL 00/11] riscv-to-apply queue, Alistair Francis, 2021/07/12
- [PULL 01/11] target/riscv: pmp: Fix some typos, Alistair Francis, 2021/07/12
- [PULL 07/11] hw/riscv: sifive_u: Correct the CLINT timebase frequency, Alistair Francis, 2021/07/12
- [PULL 03/11] docs/system: riscv: Fix CLINT name in the sifive_u doc, Alistair Francis, 2021/07/12
- [PULL 02/11] target/riscv: csr: Remove redundant check in fp csr read/write routines, Alistair Francis, 2021/07/12
- [PULL 08/11] hw/riscv: sifive_u: Make sure firmware info is 8-byte aligned, Alistair Francis, 2021/07/12
- [PULL 04/11] docs/system: riscv: Add documentation for virt machine, Alistair Francis, 2021/07/12
- [PULL 09/11] char: ibex_uart: Update the register layout,
Alistair Francis <=
- [PULL 06/11] docs/system: riscv: Update Microchip Icicle Kit for direct kernel boot, Alistair Francis, 2021/07/12
- [PULL 05/11] target/riscv: hardwire bits in hideleg and hedeleg, Alistair Francis, 2021/07/12
- [PULL 10/11] hw/riscv: opentitan: Add the unimplement rv_core_ibex_peri, Alistair Francis, 2021/07/12
- [PULL 11/11] hw/riscv: opentitan: Add the flash alias, Alistair Francis, 2021/07/12
- Re: [PULL 00/11] riscv-to-apply queue, Peter Maydell, 2021/07/13