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[PULL 02/11] target/riscv: csr: Remove redundant check in fp csr read/wr
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From: |
Alistair Francis |
|
Subject: |
[PULL 02/11] target/riscv: csr: Remove redundant check in fp csr read/write routines |
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Date: |
Mon, 12 Jul 2021 15:53:39 -0700 |
From: Bin Meng <bmeng.cn@gmail.com>
The following check:
if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
return -RISCV_EXCP_ILLEGAL_INST;
}
is redundant in fflags/frm/fcsr read/write routines, as the check was
already done in fs().
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210627120604.11116-1-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/csr.c | 24 ------------------------
1 file changed, 24 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index fe5628fea6..62b968326c 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -215,11 +215,6 @@ static RISCVException epmp(CPURISCVState *env, int csrno)
static RISCVException read_fflags(CPURISCVState *env, int csrno,
target_ulong *val)
{
-#if !defined(CONFIG_USER_ONLY)
- if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
- return RISCV_EXCP_ILLEGAL_INST;
- }
-#endif
*val = riscv_cpu_get_fflags(env);
return RISCV_EXCP_NONE;
}
@@ -228,9 +223,6 @@ static RISCVException write_fflags(CPURISCVState *env, int
csrno,
target_ulong val)
{
#if !defined(CONFIG_USER_ONLY)
- if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
- return RISCV_EXCP_ILLEGAL_INST;
- }
env->mstatus |= MSTATUS_FS;
#endif
riscv_cpu_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT));
@@ -240,11 +232,6 @@ static RISCVException write_fflags(CPURISCVState *env, int
csrno,
static RISCVException read_frm(CPURISCVState *env, int csrno,
target_ulong *val)
{
-#if !defined(CONFIG_USER_ONLY)
- if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
- return RISCV_EXCP_ILLEGAL_INST;
- }
-#endif
*val = env->frm;
return RISCV_EXCP_NONE;
}
@@ -253,9 +240,6 @@ static RISCVException write_frm(CPURISCVState *env, int
csrno,
target_ulong val)
{
#if !defined(CONFIG_USER_ONLY)
- if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
- return RISCV_EXCP_ILLEGAL_INST;
- }
env->mstatus |= MSTATUS_FS;
#endif
env->frm = val & (FSR_RD >> FSR_RD_SHIFT);
@@ -265,11 +249,6 @@ static RISCVException write_frm(CPURISCVState *env, int
csrno,
static RISCVException read_fcsr(CPURISCVState *env, int csrno,
target_ulong *val)
{
-#if !defined(CONFIG_USER_ONLY)
- if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
- return RISCV_EXCP_ILLEGAL_INST;
- }
-#endif
*val = (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT)
| (env->frm << FSR_RD_SHIFT);
if (vs(env, csrno) >= 0) {
@@ -283,9 +262,6 @@ static RISCVException write_fcsr(CPURISCVState *env, int
csrno,
target_ulong val)
{
#if !defined(CONFIG_USER_ONLY)
- if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
- return RISCV_EXCP_ILLEGAL_INST;
- }
env->mstatus |= MSTATUS_FS;
#endif
env->frm = (val & FSR_RD) >> FSR_RD_SHIFT;
--
2.31.1
- [PULL 00/11] riscv-to-apply queue, Alistair Francis, 2021/07/12
- [PULL 01/11] target/riscv: pmp: Fix some typos, Alistair Francis, 2021/07/12
- [PULL 07/11] hw/riscv: sifive_u: Correct the CLINT timebase frequency, Alistair Francis, 2021/07/12
- [PULL 03/11] docs/system: riscv: Fix CLINT name in the sifive_u doc, Alistair Francis, 2021/07/12
- [PULL 02/11] target/riscv: csr: Remove redundant check in fp csr read/write routines,
Alistair Francis <=
- [PULL 08/11] hw/riscv: sifive_u: Make sure firmware info is 8-byte aligned, Alistair Francis, 2021/07/12
- [PULL 04/11] docs/system: riscv: Add documentation for virt machine, Alistair Francis, 2021/07/12
- [PULL 09/11] char: ibex_uart: Update the register layout, Alistair Francis, 2021/07/12
- [PULL 06/11] docs/system: riscv: Update Microchip Icicle Kit for direct kernel boot, Alistair Francis, 2021/07/12
- [PULL 05/11] target/riscv: hardwire bits in hideleg and hedeleg, Alistair Francis, 2021/07/12
- [PULL 10/11] hw/riscv: opentitan: Add the unimplement rv_core_ibex_peri, Alistair Francis, 2021/07/12
- [PULL 11/11] hw/riscv: opentitan: Add the flash alias, Alistair Francis, 2021/07/12
- Re: [PULL 00/11] riscv-to-apply queue, Peter Maydell, 2021/07/13