[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL 11/11] hw/riscv: opentitan: Add the flash alias
|
From: |
Alistair Francis |
|
Subject: |
[PULL 11/11] hw/riscv: opentitan: Add the flash alias |
|
Date: |
Mon, 12 Jul 2021 15:53:48 -0700 |
OpenTitan has an alias of flash avaliable which is called virtual flash.
Add support for that in the QEMU model.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id:
c9cfbd2dd840fd0076877b8ea4d6dcfce60db5e9.1625801868.git.alistair.francis@wdc.com
---
include/hw/riscv/opentitan.h | 2 ++
hw/riscv/opentitan.c | 6 ++++++
2 files changed, 8 insertions(+)
diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h
index a488f5e8ec..9f93bebdac 100644
--- a/include/hw/riscv/opentitan.h
+++ b/include/hw/riscv/opentitan.h
@@ -40,6 +40,7 @@ struct LowRISCIbexSoCState {
MemoryRegion flash_mem;
MemoryRegion rom;
+ MemoryRegion flash_alias;
};
typedef struct OpenTitanState {
@@ -54,6 +55,7 @@ enum {
IBEX_DEV_ROM,
IBEX_DEV_RAM,
IBEX_DEV_FLASH,
+ IBEX_DEV_FLASH_VIRTUAL,
IBEX_DEV_UART,
IBEX_DEV_GPIO,
IBEX_DEV_SPI,
diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
index 933c211b11..36a41c8b5b 100644
--- a/hw/riscv/opentitan.c
+++ b/hw/riscv/opentitan.c
@@ -59,6 +59,7 @@ static const MemMapEntry ibex_memmap[] = {
[IBEX_DEV_NMI_GEN] = { 0x411c0000, 0x1000 },
[IBEX_DEV_OTBN] = { 0x411d0000, 0x10000 },
[IBEX_DEV_PERI] = { 0x411f0000, 0x10000 },
+ [IBEX_DEV_FLASH_VIRTUAL] = { 0x80000000, 0x80000 },
};
static void opentitan_board_init(MachineState *machine)
@@ -134,8 +135,13 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc,
Error **errp)
/* Flash memory */
memory_region_init_rom(&s->flash_mem, OBJECT(dev_soc),
"riscv.lowrisc.ibex.flash",
memmap[IBEX_DEV_FLASH].size, &error_fatal);
+ memory_region_init_alias(&s->flash_alias, OBJECT(dev_soc),
+ "riscv.lowrisc.ibex.flash_virtual",
&s->flash_mem, 0,
+ memmap[IBEX_DEV_FLASH_VIRTUAL].size);
memory_region_add_subregion(sys_mem, memmap[IBEX_DEV_FLASH].base,
&s->flash_mem);
+ memory_region_add_subregion(sys_mem, memmap[IBEX_DEV_FLASH_VIRTUAL].base,
+ &s->flash_alias);
/* PLIC */
if (!sysbus_realize(SYS_BUS_DEVICE(&s->plic), errp)) {
--
2.31.1
- [PULL 01/11] target/riscv: pmp: Fix some typos, (continued)
- [PULL 01/11] target/riscv: pmp: Fix some typos, Alistair Francis, 2021/07/12
- [PULL 07/11] hw/riscv: sifive_u: Correct the CLINT timebase frequency, Alistair Francis, 2021/07/12
- [PULL 03/11] docs/system: riscv: Fix CLINT name in the sifive_u doc, Alistair Francis, 2021/07/12
- [PULL 02/11] target/riscv: csr: Remove redundant check in fp csr read/write routines, Alistair Francis, 2021/07/12
- [PULL 08/11] hw/riscv: sifive_u: Make sure firmware info is 8-byte aligned, Alistair Francis, 2021/07/12
- [PULL 04/11] docs/system: riscv: Add documentation for virt machine, Alistair Francis, 2021/07/12
- [PULL 09/11] char: ibex_uart: Update the register layout, Alistair Francis, 2021/07/12
- [PULL 06/11] docs/system: riscv: Update Microchip Icicle Kit for direct kernel boot, Alistair Francis, 2021/07/12
- [PULL 05/11] target/riscv: hardwire bits in hideleg and hedeleg, Alistair Francis, 2021/07/12
- [PULL 10/11] hw/riscv: opentitan: Add the unimplement rv_core_ibex_peri, Alistair Francis, 2021/07/12
- [PULL 11/11] hw/riscv: opentitan: Add the flash alias,
Alistair Francis <=
- Re: [PULL 00/11] riscv-to-apply queue, Peter Maydell, 2021/07/13