[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH 14/55] target/arm: Implement MVE VCLS
From: |
Peter Maydell |
Subject: |
[PATCH 14/55] target/arm: Implement MVE VCLS |
Date: |
Mon, 7 Jun 2021 17:57:40 +0100 |
Implement the MVE VCLS insn.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/helper-mve.h | 4 ++++
target/arm/mve.decode | 1 +
target/arm/mve_helper.c | 7 +++++++
target/arm/translate-mve.c | 1 +
4 files changed, 13 insertions(+)
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
index c5c1315b161..bdd6675ea14 100644
--- a/target/arm/helper-mve.h
+++ b/target/arm/helper-mve.h
@@ -33,6 +33,10 @@ DEF_HELPER_FLAGS_3(mve_vstrb_h, TCG_CALL_NO_WG, void, env,
ptr, i32)
DEF_HELPER_FLAGS_3(mve_vstrb_w, TCG_CALL_NO_WG, void, env, ptr, i32)
DEF_HELPER_FLAGS_3(mve_vstrh_w, TCG_CALL_NO_WG, void, env, ptr, i32)
+DEF_HELPER_FLAGS_3(mve_vclsb, TCG_CALL_NO_WG, void, env, ptr, ptr)
+DEF_HELPER_FLAGS_3(mve_vclsh, TCG_CALL_NO_WG, void, env, ptr, ptr)
+DEF_HELPER_FLAGS_3(mve_vclsw, TCG_CALL_NO_WG, void, env, ptr, ptr)
+
DEF_HELPER_FLAGS_3(mve_vclzb, TCG_CALL_NO_WG, void, env, ptr, ptr)
DEF_HELPER_FLAGS_3(mve_vclzh, TCG_CALL_NO_WG, void, env, ptr, ptr)
DEF_HELPER_FLAGS_3(mve_vclzw, TCG_CALL_NO_WG, void, env, ptr, ptr)
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
index 24999bf703e..adceef91597 100644
--- a/target/arm/mve.decode
+++ b/target/arm/mve.decode
@@ -68,4 +68,5 @@ VLDR_VSTR 1110110 1 a:1 . w:1 . .... ... 111110
....... @vldr_vstr \
# Vector miscellaneous
+VCLS 1111 1111 1 . 11 .. 00 ... 0 0100 01 . 0 ... 0 @1op
VCLZ 1111 1111 1 . 11 .. 00 ... 0 0100 11 . 0 ... 0 @1op
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
index b7c44f57c09..071c9070593 100644
--- a/target/arm/mve_helper.c
+++ b/target/arm/mve_helper.c
@@ -238,6 +238,13 @@ static uint32_t mask_to_bytemask4(uint16_t mask)
mve_advance_vpt(env); \
}
+#define DO_CLS_B(N) (clrsb32(N) - 24)
+#define DO_CLS_H(N) (clrsb32(N) - 16)
+
+DO_1OP(vclsb, 1, int8_t, H1, DO_CLS_B)
+DO_1OP(vclsh, 2, int16_t, H2, DO_CLS_H)
+DO_1OP(vclsw, 4, int32_t, H4, clrsb32)
+
#define DO_CLZ_B(N) (clz32(N) - 24)
#define DO_CLZ_H(N) (clz32(N) - 16)
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
index 6bbc2df35c1..3c6897548a2 100644
--- a/target/arm/translate-mve.c
+++ b/target/arm/translate-mve.c
@@ -210,3 +210,4 @@ static bool do_1op(DisasContext *s, arg_1op *a,
MVEGenOneOpFn fn)
}
DO_1OP(VCLZ, vclz)
+DO_1OP(VCLS, vcls)
--
2.20.1
[PATCH 13/55] target/arm: Implement MVE VCLZ, Peter Maydell, 2021/06/07
[PATCH 12/55] target/arm: Implement widening/narrowing MVE VLDR/VSTR insns, Peter Maydell, 2021/06/07
[PATCH 14/55] target/arm: Implement MVE VCLS,
Peter Maydell <=
[PATCH 21/55] target/arm: Implement MVE VAND, VBIC, VORR, VORN, VEOR, Peter Maydell, 2021/06/07
[PATCH 20/55] target/arm: Implement MVE VDUP, Peter Maydell, 2021/06/07
[PATCH 32/55] target/arm: Implement MVE VRMLALDAVH, VRMLSLDAVH, Peter Maydell, 2021/06/07