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[PULL v2 09/42] target/riscv: Convert the RISC-V exceptions to an enum
From: |
Alistair Francis |
Subject: |
[PULL v2 09/42] target/riscv: Convert the RISC-V exceptions to an enum |
Date: |
Thu, 6 May 2021 09:22:39 +1000 |
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
f191dcf08bf413a822e743a7c7f824d68879a527.1617290165.git.alistair.francis@wdc.com
---
target/riscv/cpu_bits.h | 44 ++++++++++++++++++++-------------------
target/riscv/cpu.c | 2 +-
target/riscv/cpu_helper.c | 4 ++--
3 files changed, 26 insertions(+), 24 deletions(-)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index b42dd4f8d8..8549d77b4f 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -504,27 +504,29 @@
#define DEFAULT_RSTVEC 0x1000
/* Exception causes */
-#define EXCP_NONE -1 /* sentinel value */
-#define RISCV_EXCP_INST_ADDR_MIS 0x0
-#define RISCV_EXCP_INST_ACCESS_FAULT 0x1
-#define RISCV_EXCP_ILLEGAL_INST 0x2
-#define RISCV_EXCP_BREAKPOINT 0x3
-#define RISCV_EXCP_LOAD_ADDR_MIS 0x4
-#define RISCV_EXCP_LOAD_ACCESS_FAULT 0x5
-#define RISCV_EXCP_STORE_AMO_ADDR_MIS 0x6
-#define RISCV_EXCP_STORE_AMO_ACCESS_FAULT 0x7
-#define RISCV_EXCP_U_ECALL 0x8
-#define RISCV_EXCP_S_ECALL 0x9
-#define RISCV_EXCP_VS_ECALL 0xa
-#define RISCV_EXCP_M_ECALL 0xb
-#define RISCV_EXCP_INST_PAGE_FAULT 0xc /* since: priv-1.10.0 */
-#define RISCV_EXCP_LOAD_PAGE_FAULT 0xd /* since: priv-1.10.0 */
-#define RISCV_EXCP_STORE_PAGE_FAULT 0xf /* since: priv-1.10.0 */
-#define RISCV_EXCP_SEMIHOST 0x10
-#define RISCV_EXCP_INST_GUEST_PAGE_FAULT 0x14
-#define RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT 0x15
-#define RISCV_EXCP_VIRT_INSTRUCTION_FAULT 0x16
-#define RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT 0x17
+typedef enum RISCVException {
+ RISCV_EXCP_NONE = -1, /* sentinel value */
+ RISCV_EXCP_INST_ADDR_MIS = 0x0,
+ RISCV_EXCP_INST_ACCESS_FAULT = 0x1,
+ RISCV_EXCP_ILLEGAL_INST = 0x2,
+ RISCV_EXCP_BREAKPOINT = 0x3,
+ RISCV_EXCP_LOAD_ADDR_MIS = 0x4,
+ RISCV_EXCP_LOAD_ACCESS_FAULT = 0x5,
+ RISCV_EXCP_STORE_AMO_ADDR_MIS = 0x6,
+ RISCV_EXCP_STORE_AMO_ACCESS_FAULT = 0x7,
+ RISCV_EXCP_U_ECALL = 0x8,
+ RISCV_EXCP_S_ECALL = 0x9,
+ RISCV_EXCP_VS_ECALL = 0xa,
+ RISCV_EXCP_M_ECALL = 0xb,
+ RISCV_EXCP_INST_PAGE_FAULT = 0xc, /* since: priv-1.10.0 */
+ RISCV_EXCP_LOAD_PAGE_FAULT = 0xd, /* since: priv-1.10.0 */
+ RISCV_EXCP_STORE_PAGE_FAULT = 0xf, /* since: priv-1.10.0 */
+ RISCV_EXCP_SEMIHOST = 0x10,
+ RISCV_EXCP_INST_GUEST_PAGE_FAULT = 0x14,
+ RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT = 0x15,
+ RISCV_EXCP_VIRT_INSTRUCTION_FAULT = 0x16,
+ RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT = 0x17,
+} RISCVException;
#define RISCV_EXCP_INT_FLAG 0x80000000
#define RISCV_EXCP_INT_MASK 0x7fffffff
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 6842626c69..e530df9385 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -358,7 +358,7 @@ static void riscv_cpu_reset(DeviceState *dev)
env->pc = env->resetvec;
env->two_stage_lookup = false;
#endif
- cs->exception_index = EXCP_NONE;
+ cs->exception_index = RISCV_EXCP_NONE;
env->load_res = -1;
set_default_nan_mode(1, &env->fp_status);
}
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 503c2559f8..99cc388db9 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -72,7 +72,7 @@ static int riscv_cpu_local_irq_pending(CPURISCVState *env)
if (irqs) {
return ctz64(irqs); /* since non-zero */
} else {
- return EXCP_NONE; /* indicates no pending interrupt */
+ return RISCV_EXCP_NONE; /* indicates no pending interrupt */
}
}
#endif
@@ -1069,5 +1069,5 @@ void riscv_cpu_do_interrupt(CPUState *cs)
env->two_stage_lookup = false;
#endif
- cs->exception_index = EXCP_NONE; /* mark handled to qemu */
+ cs->exception_index = RISCV_EXCP_NONE; /* mark handled to qemu */
}
--
2.31.1
- [PULL v2 00/42] riscv-to-apply queue, Alistair Francis, 2021/05/05
- [PULL v2 01/42] target/riscv: Remove privilege v1.9 specific CSR related code, Alistair Francis, 2021/05/05
- [PULL v2 02/42] docs/system/generic-loader.rst: Fix style, Alistair Francis, 2021/05/05
- [PULL v2 03/42] target/riscv: Align the data type of reset vector address, Alistair Francis, 2021/05/05
- [PULL v2 04/42] hw/riscv: sifive_e: Add 'const' to sifive_e_memmap[], Alistair Francis, 2021/05/05
- [PULL v2 05/42] target/riscv: Add Shakti C class CPU, Alistair Francis, 2021/05/05
- [PULL v2 06/42] riscv: Add initial support for Shakti C machine, Alistair Francis, 2021/05/05
- [PULL v2 07/42] hw/char: Add Shakti UART emulation, Alistair Francis, 2021/05/05
- [PULL v2 08/42] hw/riscv: Connect Shakti UART to Shakti platform, Alistair Francis, 2021/05/05
- [PULL v2 09/42] target/riscv: Convert the RISC-V exceptions to an enum,
Alistair Francis <=
- [PULL v2 10/42] target/riscv: Use the RISCVException enum for CSR predicates, Alistair Francis, 2021/05/05
- [PULL v2 11/42] target/riscv: Fix 32-bit HS mode access permissions, Alistair Francis, 2021/05/05
- [PULL v2 12/42] target/riscv: Use the RISCVException enum for CSR operations, Alistair Francis, 2021/05/05
- [PULL v2 14/42] MAINTAINERS: Update the RISC-V CPU Maintainers, Alistair Francis, 2021/05/05
- [PULL v2 13/42] target/riscv: Use RISCVException enum for CSR access, Alistair Francis, 2021/05/05
- [PULL v2 15/42] hw/opentitan: Update the interrupt layout, Alistair Francis, 2021/05/05
- [PULL v2 16/42] hw/riscv: Enable VIRTIO_VGA for RISC-V virt machine, Alistair Francis, 2021/05/05
- [PULL v2 17/42] riscv: don't look at SUM when accessing memory from a debugger context, Alistair Francis, 2021/05/05
- [PULL v2 18/42] target/riscv: Fixup saturate subtract function, Alistair Francis, 2021/05/05
- [PULL v2 19/42] docs: Add documentation for shakti_c machine, Alistair Francis, 2021/05/05