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[PULL v2 05/42] target/riscv: Add Shakti C class CPU
From: |
Alistair Francis |
Subject: |
[PULL v2 05/42] target/riscv: Add Shakti C class CPU |
Date: |
Thu, 6 May 2021 09:22:35 +1000 |
From: Vijai Kumar K <vijai@behindbytes.com>
C-Class is a member of the SHAKTI family of processors from IIT-M.
It is an extremely configurable and commercial-grade 5-stage in-order
core supporting the standard RV64GCSUN ISA extensions.
Signed-off-by: Vijai Kumar K <vijai@behindbytes.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210401181457.73039-2-vijai@behindbytes.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 1 +
target/riscv/cpu.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 311b1db875..8079da8fa8 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -38,6 +38,7 @@
#define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32")
#define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64")
#define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex")
+#define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c")
#define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31")
#define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34")
#define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51")
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 047d6344fe..6842626c69 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -708,6 +708,7 @@ static const TypeInfo riscv_cpu_type_infos[] = {
DEFINE_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init),
+ DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init),
#endif
};
--
2.31.1
- [PULL v2 00/42] riscv-to-apply queue, Alistair Francis, 2021/05/05
- [PULL v2 01/42] target/riscv: Remove privilege v1.9 specific CSR related code, Alistair Francis, 2021/05/05
- [PULL v2 02/42] docs/system/generic-loader.rst: Fix style, Alistair Francis, 2021/05/05
- [PULL v2 03/42] target/riscv: Align the data type of reset vector address, Alistair Francis, 2021/05/05
- [PULL v2 04/42] hw/riscv: sifive_e: Add 'const' to sifive_e_memmap[], Alistair Francis, 2021/05/05
- [PULL v2 05/42] target/riscv: Add Shakti C class CPU,
Alistair Francis <=
- [PULL v2 06/42] riscv: Add initial support for Shakti C machine, Alistair Francis, 2021/05/05
- [PULL v2 07/42] hw/char: Add Shakti UART emulation, Alistair Francis, 2021/05/05
- [PULL v2 08/42] hw/riscv: Connect Shakti UART to Shakti platform, Alistair Francis, 2021/05/05
- [PULL v2 09/42] target/riscv: Convert the RISC-V exceptions to an enum, Alistair Francis, 2021/05/05
- [PULL v2 10/42] target/riscv: Use the RISCVException enum for CSR predicates, Alistair Francis, 2021/05/05
- [PULL v2 11/42] target/riscv: Fix 32-bit HS mode access permissions, Alistair Francis, 2021/05/05
- [PULL v2 12/42] target/riscv: Use the RISCVException enum for CSR operations, Alistair Francis, 2021/05/05
- [PULL v2 14/42] MAINTAINERS: Update the RISC-V CPU Maintainers, Alistair Francis, 2021/05/05
- [PULL v2 13/42] target/riscv: Use RISCVException enum for CSR access, Alistair Francis, 2021/05/05
- [PULL v2 15/42] hw/opentitan: Update the interrupt layout, Alistair Francis, 2021/05/05