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[PULL v2 19/42] docs: Add documentation for shakti_c machine
From: |
Alistair Francis |
Subject: |
[PULL v2 19/42] docs: Add documentation for shakti_c machine |
Date: |
Thu, 6 May 2021 09:22:49 +1000 |
From: Vijai Kumar K <vijai@behindbytes.com>
Add documentation for Shakti C reference platform.
Signed-off-by: Vijai Kumar K <vijai@behindbytes.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210412174248.8668-1-vijai@behindbytes.com
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
[ Changes from Bin Meng:
- Add missing TOC
Message-id: 20210430070534.1487242-1-bmeng.cn@gmail.com
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
docs/system/riscv/shakti-c.rst | 82 ++++++++++++++++++++++++++++++++++
docs/system/target-riscv.rst | 1 +
2 files changed, 83 insertions(+)
create mode 100644 docs/system/riscv/shakti-c.rst
diff --git a/docs/system/riscv/shakti-c.rst b/docs/system/riscv/shakti-c.rst
new file mode 100644
index 0000000000..a6035d42b0
--- /dev/null
+++ b/docs/system/riscv/shakti-c.rst
@@ -0,0 +1,82 @@
+Shakti C Reference Platform (``shakti_c``)
+==========================================
+
+Shakti C Reference Platform is a reference platform based on arty a7 100t
+for the Shakti SoC.
+
+Shakti SoC is a SoC based on the Shakti C-class processor core. Shakti C
+is a 64bit RV64GCSUN processor core.
+
+For more details on Shakti SoC, please see:
+https://gitlab.com/shaktiproject/cores/shakti-soc/-/blob/master/fpga/boards/artya7-100t/c-class/README.rst
+
+For more info on the Shakti C-class core, please see:
+https://c-class.readthedocs.io/en/latest/
+
+Supported devices
+-----------------
+
+The ``shakti_c`` machine supports the following devices:
+
+ * 1 C-class core
+ * Core Level Interruptor (CLINT)
+ * Platform-Level Interrupt Controller (PLIC)
+ * 1 UART
+
+Boot options
+------------
+
+The ``shakti_c`` machine can start using the standard -bios
+functionality for loading the baremetal application or opensbi.
+
+Boot the machine
+----------------
+
+Shakti SDK
+~~~~~~~~~~
+Shakti SDK can be used to generate the baremetal example UART applications.
+
+.. code-block:: bash
+
+ $ git clone https://gitlab.com/behindbytes/shakti-sdk.git
+ $ cd shakti-sdk
+ $ make software PROGRAM=loopback TARGET=artix7_100t
+
+Binary would be generated in:
+ software/examples/uart_applns/loopback/output/loopback.shakti
+
+You could also download the precompiled example applicatons using below
+commands.
+
+.. code-block:: bash
+
+ $ wget -c
https://gitlab.com/behindbytes/shakti-binaries/-/raw/master/sdk/shakti_sdk_qemu.zip
+ $ unzip shakti_sdk_qemu.zip
+
+Then we can run the UART example using:
+
+.. code-block:: bash
+
+ $ qemu-system-riscv64 -M shakti_c -nographic \
+ -bios path/to/shakti_sdk_qemu/loopback.shakti
+
+OpenSBI
+~~~~~~~
+We can also run OpenSBI with Test Payload.
+
+.. code-block:: bash
+
+ $ git clone https://github.com/riscv/opensbi.git -b v0.9
+ $ cd opensbi
+ $ wget -c
https://gitlab.com/behindbytes/shakti-binaries/-/raw/master/dts/shakti.dtb
+ $ export CROSS_COMPILE=riscv64-unknown-elf-
+ $ export FW_FDT_PATH=./shakti.dtb
+ $ make PLATFORM=generic
+
+fw_payload.elf would be generated in
build/platform/generic/firmware/fw_payload.elf.
+Boot it using the below qemu command.
+
+.. code-block:: bash
+
+ $ qemu-system-riscv64 -M shakti_c -nographic \
+ -bios path/to/fw_payload.elf
diff --git a/docs/system/target-riscv.rst b/docs/system/target-riscv.rst
index 8d5946fbbb..4b3c78382c 100644
--- a/docs/system/target-riscv.rst
+++ b/docs/system/target-riscv.rst
@@ -67,6 +67,7 @@ undocumented; you can get a complete list by running
:maxdepth: 1
riscv/microchip-icicle-kit
+ riscv/shakti-c
riscv/sifive_u
RISC-V CPU features
--
2.31.1
- [PULL v2 09/42] target/riscv: Convert the RISC-V exceptions to an enum, (continued)
- [PULL v2 09/42] target/riscv: Convert the RISC-V exceptions to an enum, Alistair Francis, 2021/05/05
- [PULL v2 10/42] target/riscv: Use the RISCVException enum for CSR predicates, Alistair Francis, 2021/05/05
- [PULL v2 11/42] target/riscv: Fix 32-bit HS mode access permissions, Alistair Francis, 2021/05/05
- [PULL v2 12/42] target/riscv: Use the RISCVException enum for CSR operations, Alistair Francis, 2021/05/05
- [PULL v2 14/42] MAINTAINERS: Update the RISC-V CPU Maintainers, Alistair Francis, 2021/05/05
- [PULL v2 13/42] target/riscv: Use RISCVException enum for CSR access, Alistair Francis, 2021/05/05
- [PULL v2 15/42] hw/opentitan: Update the interrupt layout, Alistair Francis, 2021/05/05
- [PULL v2 16/42] hw/riscv: Enable VIRTIO_VGA for RISC-V virt machine, Alistair Francis, 2021/05/05
- [PULL v2 17/42] riscv: don't look at SUM when accessing memory from a debugger context, Alistair Francis, 2021/05/05
- [PULL v2 18/42] target/riscv: Fixup saturate subtract function, Alistair Francis, 2021/05/05
- [PULL v2 19/42] docs: Add documentation for shakti_c machine,
Alistair Francis <=
- [PULL v2 20/42] target/riscv: Fix the PMP is locked check when using TOR, Alistair Francis, 2021/05/05
- [PULL v2 21/42] target/riscv: Define ePMP mseccfg, Alistair Francis, 2021/05/05
- [PULL v2 22/42] target/riscv: Add the ePMP feature, Alistair Francis, 2021/05/05
- [PULL v2 23/42] target/riscv: Add ePMP CSR access functions, Alistair Francis, 2021/05/05
- [PULL v2 24/42] target/riscv: Implementation of enhanced PMP (ePMP), Alistair Francis, 2021/05/05
- [PULL v2 25/42] target/riscv: Add a config option for ePMP, Alistair Francis, 2021/05/05
- [PULL v2 26/42] target/riscv/pmp: Remove outdated comment, Alistair Francis, 2021/05/05
- [PULL v2 27/42] target/riscv: Add ePMP support for the Ibex CPU, Alistair Francis, 2021/05/05
- [PULL v2 28/42] target/riscv: fix vrgather macro index variable type bug, Alistair Francis, 2021/05/05
- [PULL v2 29/42] target/riscv: fix exception index on instruction access fault, Alistair Francis, 2021/05/05