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[PULL 19/43] target/arm: Move TBFLAG_ANY bits to the bottom
From: |
Peter Maydell |
Subject: |
[PULL 19/43] target/arm: Move TBFLAG_ANY bits to the bottom |
Date: |
Fri, 30 Apr 2021 11:34:13 +0100 |
From: Richard Henderson <richard.henderson@linaro.org>
Now that other bits have been moved out of tb->flags,
there's no point in filling from the top.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210419202257.161730-10-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpu.h | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 15104e14409..5e0131be1a2 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3405,15 +3405,15 @@ typedef ARMCPU ArchCPU;
*
* Unless otherwise noted, these bits are cached in env->hflags.
*/
-FIELD(TBFLAG_ANY, AARCH64_STATE, 31, 1)
-FIELD(TBFLAG_ANY, SS_ACTIVE, 30, 1)
-FIELD(TBFLAG_ANY, PSTATE__SS, 29, 1) /* Not cached. */
-FIELD(TBFLAG_ANY, BE_DATA, 28, 1)
-FIELD(TBFLAG_ANY, MMUIDX, 24, 4)
+FIELD(TBFLAG_ANY, AARCH64_STATE, 0, 1)
+FIELD(TBFLAG_ANY, SS_ACTIVE, 1, 1)
+FIELD(TBFLAG_ANY, PSTATE__SS, 2, 1) /* Not cached. */
+FIELD(TBFLAG_ANY, BE_DATA, 3, 1)
+FIELD(TBFLAG_ANY, MMUIDX, 4, 4)
/* Target EL if we take a floating-point-disabled exception */
-FIELD(TBFLAG_ANY, FPEXC_EL, 22, 2)
+FIELD(TBFLAG_ANY, FPEXC_EL, 8, 2)
/* For A-profile only, target EL for debug exceptions. */
-FIELD(TBFLAG_ANY, DEBUG_TARGET_EL, 20, 2)
+FIELD(TBFLAG_ANY, DEBUG_TARGET_EL, 10, 2)
/*
* Bit usage when in AArch32 state, both A- and M-profile.
--
2.20.1
- [PULL 11/43] target/arm: Remove log2_esize parameter to gen_mte_checkN, (continued)
- [PULL 11/43] target/arm: Remove log2_esize parameter to gen_mte_checkN, Peter Maydell, 2021/04/30
- [PULL 07/43] target/arm: Replace MTEDESC ESIZE+TSIZE with SIZEM1, Peter Maydell, 2021/04/30
- [PULL 12/43] target/arm: Fix decode of align in VLDST_single, Peter Maydell, 2021/04/30
- [PULL 13/43] target/arm: Rename TBFLAG_A32, SCTLR_B, Peter Maydell, 2021/04/30
- [PULL 09/43] target/arm: Rename mte_probe1 to mte_probe, Peter Maydell, 2021/04/30
- [PULL 08/43] target/arm: Merge mte_check1, mte_checkN, Peter Maydell, 2021/04/30
- [PULL 10/43] target/arm: Simplify sve mte checking, Peter Maydell, 2021/04/30
- [PULL 14/43] target/arm: Rename TBFLAG_ANY, PSTATE_SS, Peter Maydell, 2021/04/30
- [PULL 15/43] target/arm: Add wrapper macros for accessing tbflags, Peter Maydell, 2021/04/30
- [PULL 17/43] target/arm: Move mode specific TB flags to tb->cs_base, Peter Maydell, 2021/04/30
- [PULL 19/43] target/arm: Move TBFLAG_ANY bits to the bottom,
Peter Maydell <=
- [PULL 20/43] target/arm: Add ALIGN_MEM to TBFLAG_ANY, Peter Maydell, 2021/04/30
- [PULL 21/43] target/arm: Adjust gen_aa32_{ld, st}_i32 for align+endianness, Peter Maydell, 2021/04/30
- [PULL 26/43] target/arm: Enforce alignment for LDA/LDAH/STL/STLH, Peter Maydell, 2021/04/30
- [PULL 18/43] target/arm: Move TBFLAG_AM32 bits to the top, Peter Maydell, 2021/04/30
- [PULL 22/43] target/arm: Merge gen_aa32_frob64 into gen_aa32_ld_i64, Peter Maydell, 2021/04/30
- [PULL 25/43] target/arm: Enforce word alignment for LDRD/STRD, Peter Maydell, 2021/04/30
- [PULL 29/43] target/arm: Enforce alignment for SRS, Peter Maydell, 2021/04/30
- [PULL 16/43] target/arm: Introduce CPUARMTBFlags, Peter Maydell, 2021/04/30
- [PULL 24/43] target/arm: Adjust gen_aa32_{ld, st}_i64 for align+endianness, Peter Maydell, 2021/04/30
- [PULL 31/43] target/arm: Enforce alignment for VLDR/VSTR, Peter Maydell, 2021/04/30