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[PULL 11/43] target/arm: Remove log2_esize parameter to gen_mte_checkN
From: |
Peter Maydell |
Subject: |
[PULL 11/43] target/arm: Remove log2_esize parameter to gen_mte_checkN |
Date: |
Fri, 30 Apr 2021 11:34:05 +0100 |
From: Richard Henderson <richard.henderson@linaro.org>
The log2_esize parameter is not used except trivially.
Drop the parameter and the deferral to gen_mte_check1.
This fixes a bug in that the parameters as documented
in the header file were the reverse from those in the
implementation. Which meant that translate-sve.c was
passing the parameters in the wrong order.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210416183106.1516563-10-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/translate-a64.h | 2 +-
target/arm/translate-a64.c | 15 +++++++--------
target/arm/translate-sve.c | 4 ++--
3 files changed, 10 insertions(+), 11 deletions(-)
diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h
index 3668b671ddb..868d3550486 100644
--- a/target/arm/translate-a64.h
+++ b/target/arm/translate-a64.h
@@ -44,7 +44,7 @@ TCGv_i64 clean_data_tbi(DisasContext *s, TCGv_i64 addr);
TCGv_i64 gen_mte_check1(DisasContext *s, TCGv_i64 addr, bool is_write,
bool tag_checked, int log2_size);
TCGv_i64 gen_mte_checkN(DisasContext *s, TCGv_i64 addr, bool is_write,
- bool tag_checked, int count, int log2_esize);
+ bool tag_checked, int size);
/* We should have at some point before trying to access an FP register
* done the necessary access check, so assert that
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index a68d5dd5d13..f35a5e81746 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -295,9 +295,9 @@ TCGv_i64 gen_mte_check1(DisasContext *s, TCGv_i64 addr,
bool is_write,
* For MTE, check multiple logical sequential accesses.
*/
TCGv_i64 gen_mte_checkN(DisasContext *s, TCGv_i64 addr, bool is_write,
- bool tag_checked, int log2_esize, int total_size)
+ bool tag_checked, int size)
{
- if (tag_checked && s->mte_active[0] && total_size != (1 << log2_esize)) {
+ if (tag_checked && s->mte_active[0]) {
TCGv_i32 tcg_desc;
TCGv_i64 ret;
int desc = 0;
@@ -306,7 +306,7 @@ TCGv_i64 gen_mte_checkN(DisasContext *s, TCGv_i64 addr,
bool is_write,
desc = FIELD_DP32(desc, MTEDESC, TBI, s->tbid);
desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma);
desc = FIELD_DP32(desc, MTEDESC, WRITE, is_write);
- desc = FIELD_DP32(desc, MTEDESC, SIZEM1, total_size - 1);
+ desc = FIELD_DP32(desc, MTEDESC, SIZEM1, size - 1);
tcg_desc = tcg_const_i32(desc);
ret = new_tmp_a64(s);
@@ -315,7 +315,7 @@ TCGv_i64 gen_mte_checkN(DisasContext *s, TCGv_i64 addr,
bool is_write,
return ret;
}
- return gen_mte_check1(s, addr, is_write, tag_checked, log2_esize);
+ return clean_data_tbi(s, addr);
}
typedef struct DisasCompare64 {
@@ -2965,8 +2965,7 @@ static void disas_ldst_pair(DisasContext *s, uint32_t
insn)
}
clean_addr = gen_mte_checkN(s, dirty_addr, !is_load,
- (wback || rn != 31) && !set_tag,
- size, 2 << size);
+ (wback || rn != 31) && !set_tag, 2 << size);
if (is_vector) {
if (is_load) {
@@ -3713,7 +3712,7 @@ static void disas_ldst_multiple_struct(DisasContext *s,
uint32_t insn)
* promote consecutive little-endian elements below.
*/
clean_addr = gen_mte_checkN(s, tcg_rn, is_store, is_postidx || rn != 31,
- size, total);
+ total);
/*
* Consecutive little-endian elements from a single register
@@ -3866,7 +3865,7 @@ static void disas_ldst_single_struct(DisasContext *s,
uint32_t insn)
tcg_rn = cpu_reg_sp(s, rn);
clean_addr = gen_mte_checkN(s, tcg_rn, !is_load, is_postidx || rn != 31,
- scale, total);
+ total);
tcg_ebytes = tcg_const_i64(1 << scale);
for (xs = 0; xs < selem; xs++) {
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index 5179c1f8363..584c4d047c8 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -4264,7 +4264,7 @@ static void do_ldr(DisasContext *s, uint32_t vofs, int
len, int rn, int imm)
dirty_addr = tcg_temp_new_i64();
tcg_gen_addi_i64(dirty_addr, cpu_reg_sp(s, rn), imm);
- clean_addr = gen_mte_checkN(s, dirty_addr, false, rn != 31, len, MO_8);
+ clean_addr = gen_mte_checkN(s, dirty_addr, false, rn != 31, len);
tcg_temp_free_i64(dirty_addr);
/*
@@ -4352,7 +4352,7 @@ static void do_str(DisasContext *s, uint32_t vofs, int
len, int rn, int imm)
dirty_addr = tcg_temp_new_i64();
tcg_gen_addi_i64(dirty_addr, cpu_reg_sp(s, rn), imm);
- clean_addr = gen_mte_checkN(s, dirty_addr, false, rn != 31, len, MO_8);
+ clean_addr = gen_mte_checkN(s, dirty_addr, false, rn != 31, len);
tcg_temp_free_i64(dirty_addr);
/* Note that unpredicated load/store of vector/predicate registers
--
2.20.1
- [PULL 00/43] target-arm queue, Peter Maydell, 2021/04/30
- [PULL 01/43] hw/arm/smmuv3: Support 16K translation granule, Peter Maydell, 2021/04/30
- [PULL 02/43] target/arm: Make Thumb store insns UNDEF for Rn==1111, Peter Maydell, 2021/04/30
- [PULL 03/43] target/arm: Fix mte_checkN, Peter Maydell, 2021/04/30
- [PULL 04/43] target/arm: Split out mte_probe_int, Peter Maydell, 2021/04/30
- [PULL 06/43] test/tcg/aarch64: Add mte-5, Peter Maydell, 2021/04/30
- [PULL 05/43] target/arm: Fix unaligned checks for mte_check1, mte_probe1, Peter Maydell, 2021/04/30
- [PULL 11/43] target/arm: Remove log2_esize parameter to gen_mte_checkN,
Peter Maydell <=
- [PULL 07/43] target/arm: Replace MTEDESC ESIZE+TSIZE with SIZEM1, Peter Maydell, 2021/04/30
- [PULL 12/43] target/arm: Fix decode of align in VLDST_single, Peter Maydell, 2021/04/30
- [PULL 13/43] target/arm: Rename TBFLAG_A32, SCTLR_B, Peter Maydell, 2021/04/30
- [PULL 09/43] target/arm: Rename mte_probe1 to mte_probe, Peter Maydell, 2021/04/30
- [PULL 08/43] target/arm: Merge mte_check1, mte_checkN, Peter Maydell, 2021/04/30
- [PULL 10/43] target/arm: Simplify sve mte checking, Peter Maydell, 2021/04/30
- [PULL 14/43] target/arm: Rename TBFLAG_ANY, PSTATE_SS, Peter Maydell, 2021/04/30
- [PULL 15/43] target/arm: Add wrapper macros for accessing tbflags, Peter Maydell, 2021/04/30
- [PULL 17/43] target/arm: Move mode specific TB flags to tb->cs_base, Peter Maydell, 2021/04/30
- [PULL 19/43] target/arm: Move TBFLAG_ANY bits to the bottom, Peter Maydell, 2021/04/30