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[PULL 25/43] target/arm: Enforce word alignment for LDRD/STRD
From: |
Peter Maydell |
Subject: |
[PULL 25/43] target/arm: Enforce word alignment for LDRD/STRD |
Date: |
Fri, 30 Apr 2021 11:34:19 +0100 |
From: Richard Henderson <richard.henderson@linaro.org>
Buglink: https://bugs.launchpad.net/qemu/+bug/1905356
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210419202257.161730-16-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/translate.c | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 21b241b1ced..4b0dba9e778 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -6520,13 +6520,13 @@ static bool trans_LDRD_rr(DisasContext *s, arg_ldst_rr
*a)
addr = op_addr_rr_pre(s, a);
tmp = tcg_temp_new_i32();
- gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL);
+ gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN);
store_reg(s, a->rt, tmp);
tcg_gen_addi_i32(addr, addr, 4);
tmp = tcg_temp_new_i32();
- gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL);
+ gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN);
store_reg(s, a->rt + 1, tmp);
/* LDRD w/ base writeback is undefined if the registers overlap. */
@@ -6549,13 +6549,13 @@ static bool trans_STRD_rr(DisasContext *s, arg_ldst_rr
*a)
addr = op_addr_rr_pre(s, a);
tmp = load_reg(s, a->rt);
- gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL);
+ gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN);
tcg_temp_free_i32(tmp);
tcg_gen_addi_i32(addr, addr, 4);
tmp = load_reg(s, a->rt + 1);
- gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL);
+ gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN);
tcg_temp_free_i32(tmp);
op_addr_rr_post(s, a, addr, -4);
@@ -6665,13 +6665,13 @@ static bool op_ldrd_ri(DisasContext *s, arg_ldst_ri *a,
int rt2)
addr = op_addr_ri_pre(s, a);
tmp = tcg_temp_new_i32();
- gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL);
+ gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN);
store_reg(s, a->rt, tmp);
tcg_gen_addi_i32(addr, addr, 4);
tmp = tcg_temp_new_i32();
- gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL);
+ gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN);
store_reg(s, rt2, tmp);
/* LDRD w/ base writeback is undefined if the registers overlap. */
@@ -6704,13 +6704,13 @@ static bool op_strd_ri(DisasContext *s, arg_ldst_ri *a,
int rt2)
addr = op_addr_ri_pre(s, a);
tmp = load_reg(s, a->rt);
- gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL);
+ gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN);
tcg_temp_free_i32(tmp);
tcg_gen_addi_i32(addr, addr, 4);
tmp = load_reg(s, rt2);
- gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL);
+ gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN);
tcg_temp_free_i32(tmp);
op_addr_ri_post(s, a, addr, -4);
--
2.20.1
- [PULL 10/43] target/arm: Simplify sve mte checking, (continued)
- [PULL 10/43] target/arm: Simplify sve mte checking, Peter Maydell, 2021/04/30
- [PULL 14/43] target/arm: Rename TBFLAG_ANY, PSTATE_SS, Peter Maydell, 2021/04/30
- [PULL 15/43] target/arm: Add wrapper macros for accessing tbflags, Peter Maydell, 2021/04/30
- [PULL 17/43] target/arm: Move mode specific TB flags to tb->cs_base, Peter Maydell, 2021/04/30
- [PULL 19/43] target/arm: Move TBFLAG_ANY bits to the bottom, Peter Maydell, 2021/04/30
- [PULL 20/43] target/arm: Add ALIGN_MEM to TBFLAG_ANY, Peter Maydell, 2021/04/30
- [PULL 21/43] target/arm: Adjust gen_aa32_{ld, st}_i32 for align+endianness, Peter Maydell, 2021/04/30
- [PULL 26/43] target/arm: Enforce alignment for LDA/LDAH/STL/STLH, Peter Maydell, 2021/04/30
- [PULL 18/43] target/arm: Move TBFLAG_AM32 bits to the top, Peter Maydell, 2021/04/30
- [PULL 22/43] target/arm: Merge gen_aa32_frob64 into gen_aa32_ld_i64, Peter Maydell, 2021/04/30
- [PULL 25/43] target/arm: Enforce word alignment for LDRD/STRD,
Peter Maydell <=
- [PULL 29/43] target/arm: Enforce alignment for SRS, Peter Maydell, 2021/04/30
- [PULL 16/43] target/arm: Introduce CPUARMTBFlags, Peter Maydell, 2021/04/30
- [PULL 24/43] target/arm: Adjust gen_aa32_{ld, st}_i64 for align+endianness, Peter Maydell, 2021/04/30
- [PULL 31/43] target/arm: Enforce alignment for VLDR/VSTR, Peter Maydell, 2021/04/30
- [PULL 28/43] target/arm: Enforce alignment for RFE, Peter Maydell, 2021/04/30
- [PULL 34/43] target/arm: Enforce alignment for VLDn/VSTn (single), Peter Maydell, 2021/04/30
- [PULL 39/43] target/arm: Enforce alignment for aa64 vector LDn/STn (multiple), Peter Maydell, 2021/04/30
- [PULL 36/43] target/arm: Use finalize_memop for aa64 fpr load/store, Peter Maydell, 2021/04/30
- [PULL 35/43] target/arm: Use finalize_memop for aa64 gpr load/store, Peter Maydell, 2021/04/30
- [PULL 40/43] target/arm: Enforce alignment for aa64 vector LDn/STn (single), Peter Maydell, 2021/04/30