[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL 14/16] hw/riscv: microchip_pfsoc: Map EMMC/SD mux register
From: |
Alistair Francis |
Subject: |
[PULL 14/16] hw/riscv: microchip_pfsoc: Map EMMC/SD mux register |
Date: |
Mon, 22 Mar 2021 21:57:54 -0400 |
From: Bin Meng <bin.meng@windriver.com>
Since HSS commit c20a89f8dcac, the Icicle Kit reference design has
been updated to use a register mapped at 0x4f000000 instead of a
GPIO to control whether eMMC or SD card is to be used. With this
support the same HSS image can be used for both eMMC and SD card
boot flow, while previously two different board configurations were
used. This is undocumented but one can take a look at the HSS code
HSS_MMCInit() in services/mmc/mmc_api.c.
With this commit, HSS image built from 2020.12 release boots again.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210322075248.136255-1-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
include/hw/riscv/microchip_pfsoc.h | 1 +
hw/riscv/microchip_pfsoc.c | 6 ++++++
2 files changed, 7 insertions(+)
diff --git a/include/hw/riscv/microchip_pfsoc.h
b/include/hw/riscv/microchip_pfsoc.h
index d0c666aae0..d30916f45d 100644
--- a/include/hw/riscv/microchip_pfsoc.h
+++ b/include/hw/riscv/microchip_pfsoc.h
@@ -109,6 +109,7 @@ enum {
MICROCHIP_PFSOC_ENVM_DATA,
MICROCHIP_PFSOC_QSPI_XIP,
MICROCHIP_PFSOC_IOSCB,
+ MICROCHIP_PFSOC_EMMC_SD_MUX,
MICROCHIP_PFSOC_DRAM_LO,
MICROCHIP_PFSOC_DRAM_LO_ALIAS,
MICROCHIP_PFSOC_DRAM_HI,
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index 266f1c3342..c4146b7a6b 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -122,6 +122,7 @@ static const MemMapEntry microchip_pfsoc_memmap[] = {
[MICROCHIP_PFSOC_ENVM_DATA] = { 0x20220000, 0x20000 },
[MICROCHIP_PFSOC_QSPI_XIP] = { 0x21000000, 0x1000000 },
[MICROCHIP_PFSOC_IOSCB] = { 0x30000000, 0x10000000 },
+ [MICROCHIP_PFSOC_EMMC_SD_MUX] = { 0x4f000000, 0x4 },
[MICROCHIP_PFSOC_DRAM_LO] = { 0x80000000, 0x40000000 },
[MICROCHIP_PFSOC_DRAM_LO_ALIAS] = { 0xc0000000, 0x40000000 },
[MICROCHIP_PFSOC_DRAM_HI] = { 0x1000000000, 0x0 },
@@ -411,6 +412,11 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev,
Error **errp)
sysbus_mmio_map(SYS_BUS_DEVICE(&s->ioscb), 0,
memmap[MICROCHIP_PFSOC_IOSCB].base);
+ /* eMMC/SD mux */
+ create_unimplemented_device("microchip.pfsoc.emmc_sd_mux",
+ memmap[MICROCHIP_PFSOC_EMMC_SD_MUX].base,
+ memmap[MICROCHIP_PFSOC_EMMC_SD_MUX].size);
+
/* QSPI Flash */
memory_region_init_rom(qspi_xip_mem, OBJECT(dev),
"microchip.pfsoc.qspi_xip",
--
2.30.1
- [PULL 05/16] target/riscv: flush TLB pages if PMP permission has been changed, (continued)
- [PULL 05/16] target/riscv: flush TLB pages if PMP permission has been changed, Alistair Francis, 2021/03/22
- [PULL 04/16] target/riscv: add log of PMP permission checking, Alistair Francis, 2021/03/22
- [PULL 06/16] target/riscv: Adjust privilege level for HLV(X)/HSV instructions, Alistair Francis, 2021/03/22
- [PULL 08/16] target/riscv: Use background registers also for MSTATUS_MPV, Alistair Francis, 2021/03/22
- [PULL 07/16] target/riscv: Make VSTIP and VSEIP read-only in hip, Alistair Francis, 2021/03/22
- [PULL 09/16] hw/riscv: Add fw_cfg support to virt, Alistair Francis, 2021/03/22
- [PULL 10/16] hw/riscv: allow ramfb on virt, Alistair Francis, 2021/03/22
- [PULL 11/16] target/riscv: Fix read and write accesses to vsip and vsie, Alistair Francis, 2021/03/22
- [PULL 12/16] target/riscv: Add proper two-stage lookup exception detection, Alistair Francis, 2021/03/22
- [PULL 13/16] hw/block: m25p80: Support fast read for SST flashes, Alistair Francis, 2021/03/22
- [PULL 14/16] hw/riscv: microchip_pfsoc: Map EMMC/SD mux register,
Alistair Francis <=
- [PULL 15/16] docs/system: riscv: Add documentation for 'microchip-icicle-kit' machine, Alistair Francis, 2021/03/22
- [PULL 16/16] target/riscv: Prevent lost illegal instruction exceptions, Alistair Francis, 2021/03/22
- Re: [PULL 00/16] riscv-to-apply queue, Peter Maydell, 2021/03/23