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[PULL 05/16] target/riscv: flush TLB pages if PMP permission has been ch
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From: |
Alistair Francis |
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Subject: |
[PULL 05/16] target/riscv: flush TLB pages if PMP permission has been changed |
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Date: |
Mon, 22 Mar 2021 21:57:45 -0400 |
From: Jim Shu <cwshu@andestech.com>
If PMP permission of any address has been changed by updating PMP entry,
flush all TLB pages to prevent from getting old permission.
Signed-off-by: Jim Shu <cwshu@andestech.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1613916082-19528-4-git-send-email-cwshu@andestech.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/pmp.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index ebd874cde3..cff020122a 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -28,6 +28,7 @@
#include "qapi/error.h"
#include "cpu.h"
#include "trace.h"
+#include "exec/exec-all.h"
static void pmp_write_cfg(CPURISCVState *env, uint32_t addr_index,
uint8_t val);
@@ -347,6 +348,9 @@ void pmpcfg_csr_write(CPURISCVState *env, uint32_t
reg_index,
cfg_val = (val >> 8 * i) & 0xff;
pmp_write_cfg(env, (reg_index * 4) + i, cfg_val);
}
+
+ /* If PMP permission of any addr has been changed, flush TLB pages. */
+ tlb_flush(env_cpu(env));
}
--
2.30.1
- [PULL 00/16] riscv-to-apply queue, Alistair Francis, 2021/03/22
- [PULL 01/16] target/riscv: fix vs() to return proper error code, Alistair Francis, 2021/03/22
- [PULL 02/16] hw/char: disable ibex uart receive if the buffer is full, Alistair Francis, 2021/03/22
- [PULL 03/16] target/riscv: propagate PMP permission to TLB page, Alistair Francis, 2021/03/22
- [PULL 05/16] target/riscv: flush TLB pages if PMP permission has been changed,
Alistair Francis <=
- [PULL 04/16] target/riscv: add log of PMP permission checking, Alistair Francis, 2021/03/22
- [PULL 06/16] target/riscv: Adjust privilege level for HLV(X)/HSV instructions, Alistair Francis, 2021/03/22
- [PULL 08/16] target/riscv: Use background registers also for MSTATUS_MPV, Alistair Francis, 2021/03/22
- [PULL 07/16] target/riscv: Make VSTIP and VSEIP read-only in hip, Alistair Francis, 2021/03/22
- [PULL 09/16] hw/riscv: Add fw_cfg support to virt, Alistair Francis, 2021/03/22
- [PULL 10/16] hw/riscv: allow ramfb on virt, Alistair Francis, 2021/03/22
- [PULL 11/16] target/riscv: Fix read and write accesses to vsip and vsie, Alistair Francis, 2021/03/22
- [PULL 12/16] target/riscv: Add proper two-stage lookup exception detection, Alistair Francis, 2021/03/22
- [PULL 13/16] hw/block: m25p80: Support fast read for SST flashes, Alistair Francis, 2021/03/22
- [PULL 14/16] hw/riscv: microchip_pfsoc: Map EMMC/SD mux register, Alistair Francis, 2021/03/22