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[PULL 06/16] target/riscv: Adjust privilege level for HLV(X)/HSV instruc
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From: |
Alistair Francis |
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Subject: |
[PULL 06/16] target/riscv: Adjust privilege level for HLV(X)/HSV instructions |
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Date: |
Mon, 22 Mar 2021 21:57:46 -0400 |
From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
According to the specification the "field SPVP of hstatus controls the
privilege level of the access" for the hypervisor virtual-machine load
and store instructions HLV, HLVX and HSV.
Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210311103005.1400718-1-georg.kotheimer@kernkonzept.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_helper.c | 25 ++++++++++++++-----------
1 file changed, 14 insertions(+), 11 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 0515f9aec8..b15a60d8a2 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -368,7 +368,11 @@ static int get_physical_address(CPURISCVState *env, hwaddr
*physical,
use_background = true;
}
- if (mode == PRV_M && access_type != MMU_INST_FETCH) {
+ /* MPRV does not affect the virtual-machine load/store
+ instructions, HLV, HLVX, and HSV. */
+ if (riscv_cpu_two_stage_lookup(mmu_idx)) {
+ mode = get_field(env->hstatus, HSTATUS_SPVP);
+ } else if (mode == PRV_M && access_type != MMU_INST_FETCH) {
if (get_field(env->mstatus, MSTATUS_MPRV)) {
mode = get_field(env->mstatus, MSTATUS_MPP);
}
@@ -741,19 +745,18 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int
size,
qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n",
__func__, address, access_type, mmu_idx);
- if (mode == PRV_M && access_type != MMU_INST_FETCH) {
- if (get_field(env->mstatus, MSTATUS_MPRV)) {
- mode = get_field(env->mstatus, MSTATUS_MPP);
+ /* MPRV does not affect the virtual-machine load/store
+ instructions, HLV, HLVX, and HSV. */
+ if (riscv_cpu_two_stage_lookup(mmu_idx)) {
+ mode = get_field(env->hstatus, HSTATUS_SPVP);
+ } else if (mode == PRV_M && access_type != MMU_INST_FETCH &&
+ get_field(env->mstatus, MSTATUS_MPRV)) {
+ mode = get_field(env->mstatus, MSTATUS_MPP);
+ if (riscv_has_ext(env, RVH) && get_field(env->mstatus, MSTATUS_MPV)) {
+ two_stage_lookup = true;
}
}
- if (riscv_has_ext(env, RVH) && env->priv == PRV_M &&
- access_type != MMU_INST_FETCH &&
- get_field(env->mstatus, MSTATUS_MPRV) &&
- get_field(env->mstatus, MSTATUS_MPV)) {
- two_stage_lookup = true;
- }
-
if (riscv_cpu_virt_enabled(env) ||
((riscv_cpu_two_stage_lookup(mmu_idx) || two_stage_lookup) &&
access_type != MMU_INST_FETCH)) {
--
2.30.1
- [PULL 00/16] riscv-to-apply queue, Alistair Francis, 2021/03/22
- [PULL 01/16] target/riscv: fix vs() to return proper error code, Alistair Francis, 2021/03/22
- [PULL 02/16] hw/char: disable ibex uart receive if the buffer is full, Alistair Francis, 2021/03/22
- [PULL 03/16] target/riscv: propagate PMP permission to TLB page, Alistair Francis, 2021/03/22
- [PULL 05/16] target/riscv: flush TLB pages if PMP permission has been changed, Alistair Francis, 2021/03/22
- [PULL 04/16] target/riscv: add log of PMP permission checking, Alistair Francis, 2021/03/22
- [PULL 06/16] target/riscv: Adjust privilege level for HLV(X)/HSV instructions,
Alistair Francis <=
- [PULL 08/16] target/riscv: Use background registers also for MSTATUS_MPV, Alistair Francis, 2021/03/22
- [PULL 07/16] target/riscv: Make VSTIP and VSEIP read-only in hip, Alistair Francis, 2021/03/22
- [PULL 09/16] hw/riscv: Add fw_cfg support to virt, Alistair Francis, 2021/03/22
- [PULL 10/16] hw/riscv: allow ramfb on virt, Alistair Francis, 2021/03/22
- [PULL 11/16] target/riscv: Fix read and write accesses to vsip and vsie, Alistair Francis, 2021/03/22
- [PULL 12/16] target/riscv: Add proper two-stage lookup exception detection, Alistair Francis, 2021/03/22
- [PULL 13/16] hw/block: m25p80: Support fast read for SST flashes, Alistair Francis, 2021/03/22
- [PULL 14/16] hw/riscv: microchip_pfsoc: Map EMMC/SD mux register, Alistair Francis, 2021/03/22
- [PULL 15/16] docs/system: riscv: Add documentation for 'microchip-icicle-kit' machine, Alistair Francis, 2021/03/22
- [PULL 16/16] target/riscv: Prevent lost illegal instruction exceptions, Alistair Francis, 2021/03/22