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Re: [PATCH 6/9] target/mips: Alias MSA vector registers on FPU scalar re
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From: |
Richard Henderson |
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Subject: |
Re: [PATCH 6/9] target/mips: Alias MSA vector registers on FPU scalar registers |
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Date: |
Fri, 4 Dec 2020 10:28:55 -0600 |
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User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 |
On 12/2/20 12:44 PM, Philippe Mathieu-Daudé wrote:
> Commits 863f264d10f ("add msa_reset(), global msa register") and
> cb269f273fd ("fix multiple TCG registers covering same data")
> removed the FPU scalar registers and replaced them by aliases to
> the MSA vector registers.
> While this might be the case for CPU implementing MSA, this makes
> QEMU code incoherent for CPU not implementing it. It is simpler
> to inverse the logic and alias the MSA vector registers on the
> FPU scalar ones.
How does it make things incoherent? I'm missing how the logic has actually
changed, as opposed to an order of assignments.
r~
- Re: [PATCH 1/9] target/mips: Introduce ase_msa_available() helper, (continued)
- [PATCH 2/9] target/mips: Simplify msa_reset(), Philippe Mathieu-Daudé, 2020/12/02
- [PATCH 3/9] target/mips: Use CP0_Config3 to set MIPS_HFLAG_MSA, Philippe Mathieu-Daudé, 2020/12/02
- [PATCH 4/9] target/mips: Simplify MSA TCG logic, Philippe Mathieu-Daudé, 2020/12/02
- [PATCH 5/9] target/mips: Remove now unused ASE_MSA definition, Philippe Mathieu-Daudé, 2020/12/02
- [PATCH 6/9] target/mips: Alias MSA vector registers on FPU scalar registers, Philippe Mathieu-Daudé, 2020/12/02
- Re: [PATCH 6/9] target/mips: Alias MSA vector registers on FPU scalar registers,
Richard Henderson <=
- [PATCH 7/9] target/mips: Extract msa_translate_init() from mips_tcg_init(), Philippe Mathieu-Daudé, 2020/12/02
[PATCH 8/9] target/mips: Remove CPUMIPSState* argument from gen_msa*() methods, Philippe Mathieu-Daudé, 2020/12/02
[PATCH 9/9] target/mips: Explode gen_msa_branch() as gen_msa_BxZ_V/BxZ(), Philippe Mathieu-Daudé, 2020/12/02