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Re: [PATCH 9/9] target/mips: Explode gen_msa_branch() as gen_msa_BxZ_V/B
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From: |
Richard Henderson |
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Subject: |
Re: [PATCH 9/9] target/mips: Explode gen_msa_branch() as gen_msa_BxZ_V/BxZ() |
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Date: |
Fri, 4 Dec 2020 11:04:21 -0600 |
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User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 |
On 12/2/20 12:44 PM, Philippe Mathieu-Daudé wrote:
> +static bool gen_msa_BxZ(DisasContext *ctx, int df, int wt, int s16, bool
> if_not)
> +{
> + check_msa_access(ctx);
> +
> + if (ctx->hflags & MIPS_HFLAG_BMASK) {
> + generate_exception_end(ctx, EXCP_RI);
> + return true;
> + }
> +
> + gen_check_zero_element(bcond, df, wt);
> + if (if_not) {
> + tcg_gen_setcondi_tl(TCG_COND_EQ, bcond, bcond, 0);
> + }
Since gen_check_zero_element already produces a boolean, this is better as
tcg_gen_xori_tl(bcond, bcond, if_not);
where tcg_gen_xori_tl already contains the if.
> case OPC_BNZ_D:
> - gen_check_zero_element(bcond, df, wt);
> - tcg_gen_setcondi_tl(TCG_COND_EQ, bcond, bcond, 0);
> + gen_msa_BxZ(ctx, df, wt, s16, true);
... oops, that'd be for a follow-up patch, to make this patch just code
movement.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
- Re: [PATCH 6/9] target/mips: Alias MSA vector registers on FPU scalar registers, (continued)
[PATCH 7/9] target/mips: Extract msa_translate_init() from mips_tcg_init(), Philippe Mathieu-Daudé, 2020/12/02
[PATCH 8/9] target/mips: Remove CPUMIPSState* argument from gen_msa*() methods, Philippe Mathieu-Daudé, 2020/12/02
[PATCH 9/9] target/mips: Explode gen_msa_branch() as gen_msa_BxZ_V/BxZ(), Philippe Mathieu-Daudé, 2020/12/02
- Re: [PATCH 9/9] target/mips: Explode gen_msa_branch() as gen_msa_BxZ_V/BxZ(),
Richard Henderson <=
Re: [PATCH 0/9] target/mips: Simplify MSA TCG logic, Jiaxun Yang, 2020/12/02
Re: [PATCH 0/9] target/mips: Simplify MSA TCG logic, Jiaxun Yang, 2020/12/02