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[PULL 10/29] target/arm: Split helper_crypto_sm3tt
From: |
Peter Maydell |
Subject: |
[PULL 10/29] target/arm: Split helper_crypto_sm3tt |
Date: |
Fri, 5 Jun 2020 17:49:48 +0100 |
From: Richard Henderson <richard.henderson@linaro.org>
Rather than passing an opcode to a helper, fully decode the
operation at translate time. Use clear_tail_16 to zap the
balance of the SVE register with the AdvSIMD write.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200514212831.31248-7-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/helper.h | 5 ++++-
target/arm/crypto_helper.c | 24 ++++++++++++++++++------
target/arm/translate-a64.c | 21 +++++----------------
3 files changed, 27 insertions(+), 23 deletions(-)
diff --git a/target/arm/helper.h b/target/arm/helper.h
index 13475ecf810..2a20c8174cf 100644
--- a/target/arm/helper.h
+++ b/target/arm/helper.h
@@ -531,7 +531,10 @@ DEF_HELPER_FLAGS_3(crypto_sha512su0, TCG_CALL_NO_RWG,
void, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(crypto_sha512su1, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, i32)
-DEF_HELPER_FLAGS_5(crypto_sm3tt, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32,
i32)
+DEF_HELPER_FLAGS_4(crypto_sm3tt1a, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(crypto_sm3tt1b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(crypto_sm3tt2a, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(crypto_sm3tt2b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(crypto_sm3partw1, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(crypto_sm3partw2, TCG_CALL_NO_RWG,
diff --git a/target/arm/crypto_helper.c b/target/arm/crypto_helper.c
index 636683d0f15..c76806dc8d2 100644
--- a/target/arm/crypto_helper.c
+++ b/target/arm/crypto_helper.c
@@ -632,15 +632,14 @@ void HELPER(crypto_sm3partw2)(void *vd, void *vn, void
*vm, uint32_t desc)
clear_tail_16(vd, desc);
}
-void HELPER(crypto_sm3tt)(void *vd, void *vn, void *vm, uint32_t imm2,
- uint32_t opcode)
+static inline void QEMU_ALWAYS_INLINE
+crypto_sm3tt(uint64_t *rd, uint64_t *rn, uint64_t *rm,
+ uint32_t desc, uint32_t opcode)
{
- uint64_t *rd = vd;
- uint64_t *rn = vn;
- uint64_t *rm = vm;
union CRYPTO_STATE d = { .l = { rd[0], rd[1] } };
union CRYPTO_STATE n = { .l = { rn[0], rn[1] } };
union CRYPTO_STATE m = { .l = { rm[0], rm[1] } };
+ uint32_t imm2 = simd_data(desc);
uint32_t t;
assert(imm2 < 4);
@@ -655,7 +654,7 @@ void HELPER(crypto_sm3tt)(void *vd, void *vn, void *vm,
uint32_t imm2,
/* SM3TT2B */
t = cho(CR_ST_WORD(d, 3), CR_ST_WORD(d, 2), CR_ST_WORD(d, 1));
} else {
- g_assert_not_reached();
+ qemu_build_not_reached();
}
t += CR_ST_WORD(d, 0) + CR_ST_WORD(m, imm2);
@@ -680,8 +679,21 @@ void HELPER(crypto_sm3tt)(void *vd, void *vn, void *vm,
uint32_t imm2,
rd[0] = d.l[0];
rd[1] = d.l[1];
+
+ clear_tail_16(rd, desc);
}
+#define DO_SM3TT(NAME, OPCODE) \
+ void HELPER(NAME)(void *vd, void *vn, void *vm, uint32_t desc) \
+ { crypto_sm3tt(vd, vn, vm, desc, OPCODE); }
+
+DO_SM3TT(crypto_sm3tt1a, 0)
+DO_SM3TT(crypto_sm3tt1b, 1)
+DO_SM3TT(crypto_sm3tt2a, 2)
+DO_SM3TT(crypto_sm3tt2b, 3)
+
+#undef DO_SM3TT
+
static uint8_t const sm4_sbox[] = {
0xd6, 0x90, 0xe9, 0xfe, 0xcc, 0xe1, 0x3d, 0xb7,
0x16, 0xb6, 0x14, 0xc2, 0x28, 0xfb, 0x2c, 0x05,
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 3f28888cd21..a0e72ad6942 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -13866,13 +13866,15 @@ static void disas_crypto_xar(DisasContext *s,
uint32_t insn)
*/
static void disas_crypto_three_reg_imm2(DisasContext *s, uint32_t insn)
{
+ static gen_helper_gvec_3 * const fns[4] = {
+ gen_helper_crypto_sm3tt1a, gen_helper_crypto_sm3tt1b,
+ gen_helper_crypto_sm3tt2a, gen_helper_crypto_sm3tt2b,
+ };
int opcode = extract32(insn, 10, 2);
int imm2 = extract32(insn, 12, 2);
int rm = extract32(insn, 16, 5);
int rn = extract32(insn, 5, 5);
int rd = extract32(insn, 0, 5);
- TCGv_ptr tcg_rd_ptr, tcg_rn_ptr, tcg_rm_ptr;
- TCGv_i32 tcg_imm2, tcg_opcode;
if (!dc_isar_feature(aa64_sm3, s)) {
unallocated_encoding(s);
@@ -13883,20 +13885,7 @@ static void disas_crypto_three_reg_imm2(DisasContext
*s, uint32_t insn)
return;
}
- tcg_rd_ptr = vec_full_reg_ptr(s, rd);
- tcg_rn_ptr = vec_full_reg_ptr(s, rn);
- tcg_rm_ptr = vec_full_reg_ptr(s, rm);
- tcg_imm2 = tcg_const_i32(imm2);
- tcg_opcode = tcg_const_i32(opcode);
-
- gen_helper_crypto_sm3tt(tcg_rd_ptr, tcg_rn_ptr, tcg_rm_ptr, tcg_imm2,
- tcg_opcode);
-
- tcg_temp_free_ptr(tcg_rd_ptr);
- tcg_temp_free_ptr(tcg_rn_ptr);
- tcg_temp_free_ptr(tcg_rm_ptr);
- tcg_temp_free_i32(tcg_imm2);
- tcg_temp_free_i32(tcg_opcode);
+ gen_gvec_op3_ool(s, true, rd, rn, rm, imm2, fns[opcode]);
}
/* C3.6 Data processing - SIMD, inc Crypto
--
2.20.1
- [PULL 03/29] hw/input/pxa2xx_keypad: Replace hw_error() by qemu_log_mask(), (continued)
- [PULL 03/29] hw/input/pxa2xx_keypad: Replace hw_error() by qemu_log_mask(), Peter Maydell, 2020/06/05
- [PULL 04/29] hw/arm/pxa2xx: Replace printf() call by qemu_log_mask(), Peter Maydell, 2020/06/05
- [PULL 06/29] target/arm: Convert rax1 to gvec helpers, Peter Maydell, 2020/06/05
- [PULL 05/29] target/arm: Convert aes and sm4 to gvec helpers, Peter Maydell, 2020/06/05
- [PULL 07/29] target/arm: Convert sha512 and sm3 to gvec helpers, Peter Maydell, 2020/06/05
- [PULL 08/29] target/arm: Convert sha1 and sha256 to gvec helpers, Peter Maydell, 2020/06/05
- [PULL 09/29] target/arm: Split helper_crypto_sha1_3reg, Peter Maydell, 2020/06/05
- [PULL 11/29] hw/adc/stm32f2xx_adc: Correct memory region size and access size, Peter Maydell, 2020/06/05
- [PULL 13/29] docs/system: Document Aspeed boards, Peter Maydell, 2020/06/05
- [PULL 12/29] tests/acceptance: Add a boot test for the xlnx-versal-virt machine, Peter Maydell, 2020/06/05
- [PULL 10/29] target/arm: Split helper_crypto_sm3tt,
Peter Maydell <=
- [PULL 14/29] raspi: add BCM2835 SOC MPHI emulation, Peter Maydell, 2020/06/05
- [PULL 16/29] dwc-hsotg (dwc2) USB host controller state definitions, Peter Maydell, 2020/06/05
- [PULL 15/29] dwc-hsotg (dwc2) USB host controller register definitions, Peter Maydell, 2020/06/05
- [PULL 18/29] usb: add short-packet handling to usb-storage driver, Peter Maydell, 2020/06/05
- [PULL 20/29] raspi2 acceptance test: add test for dwc-hsotg (dwc2) USB host, Peter Maydell, 2020/06/05
- [PULL 17/29] dwc-hsotg (dwc2) USB host controller emulation, Peter Maydell, 2020/06/05
- [PULL 19/29] wire in the dwc-hsotg (dwc2) USB host controller emulation, Peter Maydell, 2020/06/05
- [PULL 21/29] target/arm: Convert Neon VSHL and VSLI 2-reg-shift insn to decodetree, Peter Maydell, 2020/06/05
- [PULL 23/29] target/arm: Convert Neon VSRA, VSRI, VRSHR, VRSRA 2-reg-shift insns to decodetree, Peter Maydell, 2020/06/05
- [PULL 24/29] target/arm: Convert VQSHLU, VQSHL 2-reg-shift insns to decodetree, Peter Maydell, 2020/06/05