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[PULL 11/29] hw/adc/stm32f2xx_adc: Correct memory region size and access
From: |
Peter Maydell |
Subject: |
[PULL 11/29] hw/adc/stm32f2xx_adc: Correct memory region size and access size |
Date: |
Fri, 5 Jun 2020 17:49:49 +0100 |
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
The ADC region size is 256B, split as:
- [0x00 - 0x4f] defined
- [0x50 - 0xff] reserved
All registers are 32-bit (thus when the datasheet mentions the
last defined register is 0x4c, it means its address range is
0x4c .. 0x4f.
This model implementation is also 32-bit. Set MemoryRegionOps
'impl' fields.
See:
'RM0033 Reference manual Rev 8', Table 10.13.18 "ADC register map".
Reported-by: Seth Kintigh <skintigh@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200603055915.17678-1-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/adc/stm32f2xx_adc.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/hw/adc/stm32f2xx_adc.c b/hw/adc/stm32f2xx_adc.c
index 4f9d485ecf2..01a0b14e69d 100644
--- a/hw/adc/stm32f2xx_adc.c
+++ b/hw/adc/stm32f2xx_adc.c
@@ -246,6 +246,8 @@ static const MemoryRegionOps stm32f2xx_adc_ops = {
.read = stm32f2xx_adc_read,
.write = stm32f2xx_adc_write,
.endianness = DEVICE_NATIVE_ENDIAN,
+ .impl.min_access_size = 4,
+ .impl.max_access_size = 4,
};
static const VMStateDescription vmstate_stm32f2xx_adc = {
@@ -278,7 +280,7 @@ static void stm32f2xx_adc_init(Object *obj)
sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
memory_region_init_io(&s->mmio, obj, &stm32f2xx_adc_ops, s,
- TYPE_STM32F2XX_ADC, 0xFF);
+ TYPE_STM32F2XX_ADC, 0x100);
sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
}
--
2.20.1
- [PULL 00/29] target-arm queue, Peter Maydell, 2020/06/05
- [PULL 01/29] hw/ssi/imx_spi: changed while statement to prevent underflow, Peter Maydell, 2020/06/05
- [PULL 02/29] hw/ssi/imx_spi: Removed unnecessary cast of rx data received from slave, Peter Maydell, 2020/06/05
- [PULL 03/29] hw/input/pxa2xx_keypad: Replace hw_error() by qemu_log_mask(), Peter Maydell, 2020/06/05
- [PULL 04/29] hw/arm/pxa2xx: Replace printf() call by qemu_log_mask(), Peter Maydell, 2020/06/05
- [PULL 06/29] target/arm: Convert rax1 to gvec helpers, Peter Maydell, 2020/06/05
- [PULL 05/29] target/arm: Convert aes and sm4 to gvec helpers, Peter Maydell, 2020/06/05
- [PULL 07/29] target/arm: Convert sha512 and sm3 to gvec helpers, Peter Maydell, 2020/06/05
- [PULL 08/29] target/arm: Convert sha1 and sha256 to gvec helpers, Peter Maydell, 2020/06/05
- [PULL 09/29] target/arm: Split helper_crypto_sha1_3reg, Peter Maydell, 2020/06/05
- [PULL 11/29] hw/adc/stm32f2xx_adc: Correct memory region size and access size,
Peter Maydell <=
- [PULL 13/29] docs/system: Document Aspeed boards, Peter Maydell, 2020/06/05
- [PULL 12/29] tests/acceptance: Add a boot test for the xlnx-versal-virt machine, Peter Maydell, 2020/06/05
- [PULL 10/29] target/arm: Split helper_crypto_sm3tt, Peter Maydell, 2020/06/05
- [PULL 14/29] raspi: add BCM2835 SOC MPHI emulation, Peter Maydell, 2020/06/05
- [PULL 16/29] dwc-hsotg (dwc2) USB host controller state definitions, Peter Maydell, 2020/06/05
- [PULL 15/29] dwc-hsotg (dwc2) USB host controller register definitions, Peter Maydell, 2020/06/05
- [PULL 18/29] usb: add short-packet handling to usb-storage driver, Peter Maydell, 2020/06/05
- [PULL 20/29] raspi2 acceptance test: add test for dwc-hsotg (dwc2) USB host, Peter Maydell, 2020/06/05
- [PULL 17/29] dwc-hsotg (dwc2) USB host controller emulation, Peter Maydell, 2020/06/05
- [PULL 19/29] wire in the dwc-hsotg (dwc2) USB host controller emulation, Peter Maydell, 2020/06/05