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[PULL 23/29] target/arm: Convert Neon VSRA, VSRI, VRSHR, VRSRA 2-reg-shi
From: |
Peter Maydell |
Subject: |
[PULL 23/29] target/arm: Convert Neon VSRA, VSRI, VRSHR, VRSRA 2-reg-shift insns to decodetree |
Date: |
Fri, 5 Jun 2020 17:50:01 +0100 |
Convert the VSRA, VSRI, VRSHR, VRSRA 2-reg-shift insns to decodetree.
(These are the last instructions in the group that are vectorized;
the rest all require looping over each element.)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200522145520.6778-4-peter.maydell@linaro.org
---
target/arm/neon-dp.decode | 35 ++++++++++++++++++++++
target/arm/translate-neon.inc.c | 7 +++++
target/arm/translate.c | 52 +++------------------------------
3 files changed, 46 insertions(+), 48 deletions(-)
diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
index 1b877cc68f6..659cf139303 100644
--- a/target/arm/neon-dp.decode
+++ b/target/arm/neon-dp.decode
@@ -242,6 +242,41 @@ VSHR_U_2sh 1111 001 1 1 . ...... .... 0000 . . . 1
.... @2reg_shr_s
VSHR_U_2sh 1111 001 1 1 . ...... .... 0000 . . . 1 .... @2reg_shr_h
VSHR_U_2sh 1111 001 1 1 . ...... .... 0000 . . . 1 .... @2reg_shr_b
+VSRA_S_2sh 1111 001 0 1 . ...... .... 0001 . . . 1 .... @2reg_shr_d
+VSRA_S_2sh 1111 001 0 1 . ...... .... 0001 . . . 1 .... @2reg_shr_s
+VSRA_S_2sh 1111 001 0 1 . ...... .... 0001 . . . 1 .... @2reg_shr_h
+VSRA_S_2sh 1111 001 0 1 . ...... .... 0001 . . . 1 .... @2reg_shr_b
+
+VSRA_U_2sh 1111 001 1 1 . ...... .... 0001 . . . 1 .... @2reg_shr_d
+VSRA_U_2sh 1111 001 1 1 . ...... .... 0001 . . . 1 .... @2reg_shr_s
+VSRA_U_2sh 1111 001 1 1 . ...... .... 0001 . . . 1 .... @2reg_shr_h
+VSRA_U_2sh 1111 001 1 1 . ...... .... 0001 . . . 1 .... @2reg_shr_b
+
+VRSHR_S_2sh 1111 001 0 1 . ...... .... 0010 . . . 1 .... @2reg_shr_d
+VRSHR_S_2sh 1111 001 0 1 . ...... .... 0010 . . . 1 .... @2reg_shr_s
+VRSHR_S_2sh 1111 001 0 1 . ...... .... 0010 . . . 1 .... @2reg_shr_h
+VRSHR_S_2sh 1111 001 0 1 . ...... .... 0010 . . . 1 .... @2reg_shr_b
+
+VRSHR_U_2sh 1111 001 1 1 . ...... .... 0010 . . . 1 .... @2reg_shr_d
+VRSHR_U_2sh 1111 001 1 1 . ...... .... 0010 . . . 1 .... @2reg_shr_s
+VRSHR_U_2sh 1111 001 1 1 . ...... .... 0010 . . . 1 .... @2reg_shr_h
+VRSHR_U_2sh 1111 001 1 1 . ...... .... 0010 . . . 1 .... @2reg_shr_b
+
+VRSRA_S_2sh 1111 001 0 1 . ...... .... 0011 . . . 1 .... @2reg_shr_d
+VRSRA_S_2sh 1111 001 0 1 . ...... .... 0011 . . . 1 .... @2reg_shr_s
+VRSRA_S_2sh 1111 001 0 1 . ...... .... 0011 . . . 1 .... @2reg_shr_h
+VRSRA_S_2sh 1111 001 0 1 . ...... .... 0011 . . . 1 .... @2reg_shr_b
+
+VRSRA_U_2sh 1111 001 1 1 . ...... .... 0011 . . . 1 .... @2reg_shr_d
+VRSRA_U_2sh 1111 001 1 1 . ...... .... 0011 . . . 1 .... @2reg_shr_s
+VRSRA_U_2sh 1111 001 1 1 . ...... .... 0011 . . . 1 .... @2reg_shr_h
+VRSRA_U_2sh 1111 001 1 1 . ...... .... 0011 . . . 1 .... @2reg_shr_b
+
+VSRI_2sh 1111 001 1 1 . ...... .... 0100 . . . 1 .... @2reg_shr_d
+VSRI_2sh 1111 001 1 1 . ...... .... 0100 . . . 1 .... @2reg_shr_s
+VSRI_2sh 1111 001 1 1 . ...... .... 0100 . . . 1 .... @2reg_shr_h
+VSRI_2sh 1111 001 1 1 . ...... .... 0100 . . . 1 .... @2reg_shr_b
+
VSHL_2sh 1111 001 0 1 . ...... .... 0101 . . . 1 .... @2reg_shl_d
VSHL_2sh 1111 001 0 1 . ...... .... 0101 . . . 1 .... @2reg_shl_s
VSHL_2sh 1111 001 0 1 . ...... .... 0101 . . . 1 .... @2reg_shl_h
diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
index 8693b9aa99d..28688000594 100644
--- a/target/arm/translate-neon.inc.c
+++ b/target/arm/translate-neon.inc.c
@@ -1258,6 +1258,13 @@ static bool do_vector_2sh(DisasContext *s,
arg_2reg_shift *a, GVecGen2iFn *fn)
DO_2SH(VSHL, tcg_gen_gvec_shli)
DO_2SH(VSLI, gen_gvec_sli)
+DO_2SH(VSRI, gen_gvec_sri)
+DO_2SH(VSRA_S, gen_gvec_ssra)
+DO_2SH(VSRA_U, gen_gvec_usra)
+DO_2SH(VRSHR_S, gen_gvec_srshr)
+DO_2SH(VRSHR_U, gen_gvec_urshr)
+DO_2SH(VRSRA_S, gen_gvec_srsra)
+DO_2SH(VRSRA_U, gen_gvec_ursra)
static bool trans_VSHR_S_2sh(DisasContext *s, arg_2reg_shift *a)
{
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 4acc94e3cbc..2d08c644839 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -5297,6 +5297,10 @@ static int disas_neon_data_insn(DisasContext *s,
uint32_t insn)
switch (op) {
case 0: /* VSHR */
+ case 1: /* VSRA */
+ case 2: /* VRSHR */
+ case 3: /* VRSRA */
+ case 4: /* VSRI */
case 5: /* VSHL, VSLI */
return 1; /* handled by decodetree */
default:
@@ -5330,54 +5334,6 @@ static int disas_neon_data_insn(DisasContext *s,
uint32_t insn)
shift = shift - (1 << (size + 3));
}
- switch (op) {
- case 1: /* VSRA */
- /* Right shift comes here negative. */
- shift = -shift;
- if (u) {
- gen_gvec_usra(size, rd_ofs, rm_ofs, shift,
- vec_size, vec_size);
- } else {
- gen_gvec_ssra(size, rd_ofs, rm_ofs, shift,
- vec_size, vec_size);
- }
- return 0;
-
- case 2: /* VRSHR */
- /* Right shift comes here negative. */
- shift = -shift;
- if (u) {
- gen_gvec_urshr(size, rd_ofs, rm_ofs, shift,
- vec_size, vec_size);
- } else {
- gen_gvec_srshr(size, rd_ofs, rm_ofs, shift,
- vec_size, vec_size);
- }
- return 0;
-
- case 3: /* VRSRA */
- /* Right shift comes here negative. */
- shift = -shift;
- if (u) {
- gen_gvec_ursra(size, rd_ofs, rm_ofs, shift,
- vec_size, vec_size);
- } else {
- gen_gvec_srsra(size, rd_ofs, rm_ofs, shift,
- vec_size, vec_size);
- }
- return 0;
-
- case 4: /* VSRI */
- if (!u) {
- return 1;
- }
- /* Right shift comes here negative. */
- shift = -shift;
- gen_gvec_sri(size, rd_ofs, rm_ofs, shift,
- vec_size, vec_size);
- return 0;
- }
-
if (size == 3) {
count = q + 1;
} else {
--
2.20.1
- [PULL 12/29] tests/acceptance: Add a boot test for the xlnx-versal-virt machine, (continued)
- [PULL 12/29] tests/acceptance: Add a boot test for the xlnx-versal-virt machine, Peter Maydell, 2020/06/05
- [PULL 10/29] target/arm: Split helper_crypto_sm3tt, Peter Maydell, 2020/06/05
- [PULL 14/29] raspi: add BCM2835 SOC MPHI emulation, Peter Maydell, 2020/06/05
- [PULL 16/29] dwc-hsotg (dwc2) USB host controller state definitions, Peter Maydell, 2020/06/05
- [PULL 15/29] dwc-hsotg (dwc2) USB host controller register definitions, Peter Maydell, 2020/06/05
- [PULL 18/29] usb: add short-packet handling to usb-storage driver, Peter Maydell, 2020/06/05
- [PULL 20/29] raspi2 acceptance test: add test for dwc-hsotg (dwc2) USB host, Peter Maydell, 2020/06/05
- [PULL 17/29] dwc-hsotg (dwc2) USB host controller emulation, Peter Maydell, 2020/06/05
- [PULL 19/29] wire in the dwc-hsotg (dwc2) USB host controller emulation, Peter Maydell, 2020/06/05
- [PULL 21/29] target/arm: Convert Neon VSHL and VSLI 2-reg-shift insn to decodetree, Peter Maydell, 2020/06/05
- [PULL 23/29] target/arm: Convert Neon VSRA, VSRI, VRSHR, VRSRA 2-reg-shift insns to decodetree,
Peter Maydell <=
- [PULL 24/29] target/arm: Convert VQSHLU, VQSHL 2-reg-shift insns to decodetree, Peter Maydell, 2020/06/05
- [PULL 25/29] target/arm: Convert Neon narrowing shifts with op==8 to decodetree, Peter Maydell, 2020/06/05
- [PULL 22/29] target/arm: Convert Neon VSHR 2-reg-shift insns to decodetree, Peter Maydell, 2020/06/05
- [PULL 26/29] target/arm: Convert Neon narrowing shifts with op==9 to decodetree, Peter Maydell, 2020/06/05
- [PULL 27/29] target/arm: Convert Neon VSHLL, VMOVL to decodetree, Peter Maydell, 2020/06/05
- [PULL 28/29] target/arm: Convert VCVT fixed-point ops to decodetree, Peter Maydell, 2020/06/05
- [PULL 29/29] target/arm: Convert Neon one-register-and-immediate insns to decodetree, Peter Maydell, 2020/06/05
- Re: [PULL 00/29] target-arm queue, no-reply, 2020/06/05
- Re: [PULL 00/29] target-arm queue, Peter Maydell, 2020/06/08