[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL 48/52] target/arm: Rename isar_feature_aa32_fpdp_v2
From: |
Peter Maydell |
Subject: |
[PULL 48/52] target/arm: Rename isar_feature_aa32_fpdp_v2 |
Date: |
Fri, 21 Feb 2020 13:07:36 +0000 |
From: Richard Henderson <address@hidden>
The old name, isar_feature_aa32_fpdp, does not reflect
that the test includes VFPv2. We will introduce further
feature tests for VFPv3.
Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
[PMM: fixed grammar in commit message]
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/cpu.h | 4 ++--
target/arm/translate-vfp.inc.c | 40 +++++++++++++++++-----------------
2 files changed, 22 insertions(+), 22 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 5a62586dd29..1e2aae276bf 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3467,9 +3467,9 @@ static inline bool isar_feature_aa32_fpshvec(const
ARMISARegisters *id)
return FIELD_EX32(id->mvfr0, MVFR0, FPSHVEC) > 0;
}
-static inline bool isar_feature_aa32_fpdp(const ARMISARegisters *id)
+static inline bool isar_feature_aa32_fpdp_v2(const ARMISARegisters *id)
{
- /* Return true if CPU supports double precision floating point */
+ /* Return true if CPU supports double precision floating point, VFPv2 */
return FIELD_EX32(id->mvfr0, MVFR0, FPDP) > 0;
}
diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c
index ba46e2557a1..e94876c30ca 100644
--- a/target/arm/translate-vfp.inc.c
+++ b/target/arm/translate-vfp.inc.c
@@ -206,7 +206,7 @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a)
return false;
}
- if (dp && !dc_isar_feature(aa32_fpdp, s)) {
+ if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
@@ -339,7 +339,7 @@ static bool trans_VMINMAXNM(DisasContext *s, arg_VMINMAXNM
*a)
return false;
}
- if (dp && !dc_isar_feature(aa32_fpdp, s)) {
+ if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
@@ -425,7 +425,7 @@ static bool trans_VRINT(DisasContext *s, arg_VRINT *a)
return false;
}
- if (dp && !dc_isar_feature(aa32_fpdp, s)) {
+ if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
@@ -488,7 +488,7 @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a)
return false;
}
- if (dp && !dc_isar_feature(aa32_fpdp, s)) {
+ if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
@@ -1313,7 +1313,7 @@ static bool do_vfp_3op_dp(DisasContext *s, VFPGen3OpDPFn
*fn,
return false;
}
- if (!dc_isar_feature(aa32_fpdp, s)) {
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
@@ -1462,7 +1462,7 @@ static bool do_vfp_2op_dp(DisasContext *s, VFPGen2OpDPFn
*fn, int vd, int vm)
return false;
}
- if (!dc_isar_feature(aa32_fpdp, s)) {
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
@@ -1827,7 +1827,7 @@ static bool trans_VFM_dp(DisasContext *s, arg_VFM_dp *a)
return false;
}
- if (!dc_isar_feature(aa32_fpdp, s)) {
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
@@ -1926,7 +1926,7 @@ static bool trans_VMOV_imm_dp(DisasContext *s,
arg_VMOV_imm_dp *a)
return false;
}
- if (!dc_isar_feature(aa32_fpdp, s)) {
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
@@ -2070,7 +2070,7 @@ static bool trans_VCMP_dp(DisasContext *s, arg_VCMP_dp *a)
return false;
}
- if (!dc_isar_feature(aa32_fpdp, s)) {
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
@@ -2143,7 +2143,7 @@ static bool trans_VCVT_f64_f16(DisasContext *s,
arg_VCVT_f64_f16 *a)
return false;
}
- if (!dc_isar_feature(aa32_fpdp, s)) {
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
@@ -2209,7 +2209,7 @@ static bool trans_VCVT_f16_f64(DisasContext *s,
arg_VCVT_f16_f64 *a)
return false;
}
- if (!dc_isar_feature(aa32_fpdp, s)) {
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
@@ -2269,7 +2269,7 @@ static bool trans_VRINTR_dp(DisasContext *s,
arg_VRINTR_dp *a)
return false;
}
- if (!dc_isar_feature(aa32_fpdp, s)) {
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
@@ -2330,7 +2330,7 @@ static bool trans_VRINTZ_dp(DisasContext *s,
arg_VRINTZ_dp *a)
return false;
}
- if (!dc_isar_feature(aa32_fpdp, s)) {
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
@@ -2389,7 +2389,7 @@ static bool trans_VRINTX_dp(DisasContext *s,
arg_VRINTX_dp *a)
return false;
}
- if (!dc_isar_feature(aa32_fpdp, s)) {
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
@@ -2417,7 +2417,7 @@ static bool trans_VCVT_sp(DisasContext *s, arg_VCVT_sp *a)
return false;
}
- if (!dc_isar_feature(aa32_fpdp, s)) {
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
@@ -2445,7 +2445,7 @@ static bool trans_VCVT_dp(DisasContext *s, arg_VCVT_dp *a)
return false;
}
- if (!dc_isar_feature(aa32_fpdp, s)) {
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
@@ -2499,7 +2499,7 @@ static bool trans_VCVT_int_dp(DisasContext *s,
arg_VCVT_int_dp *a)
return false;
}
- if (!dc_isar_feature(aa32_fpdp, s)) {
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
@@ -2539,7 +2539,7 @@ static bool trans_VJCVT(DisasContext *s, arg_VJCVT *a)
return false;
}
- if (!dc_isar_feature(aa32_fpdp, s)) {
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
@@ -2632,7 +2632,7 @@ static bool trans_VCVT_fix_dp(DisasContext *s,
arg_VCVT_fix_dp *a)
return false;
}
- if (!dc_isar_feature(aa32_fpdp, s)) {
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
@@ -2728,7 +2728,7 @@ static bool trans_VCVT_dp_int(DisasContext *s,
arg_VCVT_dp_int *a)
return false;
}
- if (!dc_isar_feature(aa32_fpdp, s)) {
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
--
2.20.1
- [PULL 36/52] hcd-ehci: Introduce "companion-enable" sysbus property, (continued)
- [PULL 36/52] hcd-ehci: Introduce "companion-enable" sysbus property, Peter Maydell, 2020/02/21
- [PULL 39/52] target/arm: Convert PMUL.8 to gvec, Peter Maydell, 2020/02/21
- [PULL 42/52] xilinx_spips: Correct the number of dummy cycles for the FAST_READ_4 cmd, Peter Maydell, 2020/02/21
- [PULL 40/52] target/arm: Convert PMULL.64 to gvec, Peter Maydell, 2020/02/21
- [PULL 38/52] target/arm: Vectorize USHL and SSHL, Peter Maydell, 2020/02/21
- [PULL 41/52] target/arm: Convert PMULL.8 to gvec, Peter Maydell, 2020/02/21
- [PULL 44/52] target/arm: Rename isar_feature_aa32_simd_r32, Peter Maydell, 2020/02/21
- [PULL 45/52] target/arm: Use isar_feature_aa32_simd_r32 more places, Peter Maydell, 2020/02/21
- [PULL 46/52] target/arm: Set MVFR0.FPSP for ARMv5 cpus, Peter Maydell, 2020/02/21
- [PULL 49/52] target/arm: Add isar_feature_aa32_{fpsp_v2, fpsp_v3, fpdp_v3}, Peter Maydell, 2020/02/21
- [PULL 48/52] target/arm: Rename isar_feature_aa32_fpdp_v2,
Peter Maydell <=
- [PULL 43/52] sh4: Fix PCI ISA IO memory subregion, Peter Maydell, 2020/02/21
- [PULL 47/52] target/arm: Add isar_feature_aa32_simd_r16, Peter Maydell, 2020/02/21
- [PULL 51/52] target/arm: Replace ARM_FEATURE_VFP3 checks with fp{sp, dp}_v3, Peter Maydell, 2020/02/21
- [PULL 50/52] target/arm: Perform fpdp_v2 check first, Peter Maydell, 2020/02/21
- [PULL 52/52] target/arm: Add missing checks for fpsp_v2, Peter Maydell, 2020/02/21
- Re: [PULL 00/52] target-arm queue, no-reply, 2020/02/21
- Re: [PULL 00/52] target-arm queue, no-reply, 2020/02/21
- Re: [PULL 00/52] target-arm queue, no-reply, 2020/02/21