Re: [PULL 00/52] target-arm queue

[no-reply]

Patchew URL: https://patchew.org/QEMU/address@hidden/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Subject: [PULL 00/52] target-arm queue
Message-id: address@hidden
Type: series

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

From https://github.com/patchew-project/qemu
 * [new tag]         patchew/address@hidden -> patchew/address@hidden
Auto packing the repository for optimum performance. You may also
run "git gc" manually. See "git help gc" for more information.
Switched to a new branch 'test'
ca0e9f4 target/arm: Add missing checks for fpsp_v2
27b2141 target/arm: Replace ARM_FEATURE_VFP3 checks with fp{sp, dp}_v3
c568474 target/arm: Perform fpdp_v2 check first
d0860b2 target/arm: Add isar_feature_aa32_{fpsp_v2, fpsp_v3, fpdp_v3}
2b38215 target/arm: Rename isar_feature_aa32_fpdp_v2
30aecdc target/arm: Add isar_feature_aa32_simd_r16
3429e74 target/arm: Set MVFR0.FPSP for ARMv5 cpus
15e4e4a target/arm: Use isar_feature_aa32_simd_r32 more places
bef8c86 target/arm: Rename isar_feature_aa32_simd_r32
96f7694 sh4: Fix PCI ISA IO memory subregion
aa6e40e xilinx_spips: Correct the number of dummy cycles for the FAST_READ_4 cmd
4d6c390 target/arm: Convert PMULL.8 to gvec
905fba6 target/arm: Convert PMULL.64 to gvec
70b0557 target/arm: Convert PMUL.8 to gvec
a05bc4b target/arm: Vectorize USHL and SSHL
c1ae8a0 arm: allwinner: Wire up USB ports
fa553eb hcd-ehci: Introduce "companion-enable" sysbus property
2d78af3 hw: usb: hcd-ohci: Move OHCISysBusState and TYPE_SYSBUS_OHCI to include 
file
50cb694 target/arm: Correctly implement ACTLR2, HACTLR2
d23b72b target/arm: Use FIELD_EX32 for testing 32-bit fields
e2fa093 target/arm: Use isar_feature function for testing AA32HPD feature
64cfed1 target/arm: Test correct register in aa32_pan and aa32_ats1e1 checks
c8f037c target/arm: Correct handling of PMCR_EL0.LC bit
653df0e target/arm: Correct definition of PMCRDP
3bb509d target/arm: Provide ARMv8.4-PMU in '-cpu max'
bff845e target/arm: Implement ARMv8.4-PMU extension
0774d69 target/arm: Implement ARMv8.1-PMU extension
80bc213 target/arm: Read debug-related ID registers from KVM
a269f0b target/arm: Move DBGDIDR into ARMISARegisters
258a687 target/arm: Stop assuming DBGDIDR always exists
6e40c83 target/arm: Add _aa64_ and _any_ versions of pmu_8_1 isar checks
579bcd1 target/arm: Define an aa32_pmu_8_1 isar feature test function
5915825 target/arm: Use FIELD macros for clearing ID_DFR0 PERFMON field
43e317f target/arm: Add and use FIELD definitions for ID_AA64DFR0_EL1
48acad9 target/arm: Factor out PMU register definitions
ee54430 target/arm: Define and use any_predinv isar_feature test
d46a14b target/arm: Add isar_feature_any_fp16 and document naming/usage 
conventions
763de40 target/arm: Check aa32_pan in take_aarch32_exception(), not aa64_pan
1d8dc7e target/arm: Add _aa32_ to isar_feature functions testing 32-bit ID 
registers
8671014 target/arm: Split out aa64_va_parameter_tbi, aa64_va_parameter_tbid
96873ae target/arm: Remove ttbr1_valid check from get_phys_addr_lpae
d130aa3 target/arm: Fix select for aa64_va_parameters_both
9bac411 target/arm: Use bit 55 explicitly for pauth
5c7354e target/arm: Flush high bits of sve register after AdvSIMD INS
d065942 target/arm: Flush high bits of sve register after AdvSIMD ZIP/UZP/TRN
8612c53 target/arm: Flush high bits of sve register after AdvSIMD TBL/TBX
0f3e066 target/arm: Flush high bits of sve register after AdvSIMD EXT
f74d35c z2: Make providing flash images non-mandatory
632d45e mainstone: Make providing flash images non-mandatory
2975095 hw/misc/iotkit-secctl: Fix writing to 'PPC Interrupt Clear' register
e69e280 aspeed/scu: Implement chip ID register
01813ea aspeed/scu: Create separate write callbacks

=== OUTPUT BEGIN ===
1/52 Checking commit 01813ea2ce7a (aspeed/scu: Create separate write callbacks)
2/52 Checking commit e69e2806a7c3 (aspeed/scu: Implement chip ID register)
3/52 Checking commit 297509546899 (hw/misc/iotkit-secctl: Fix writing to 'PPC 
Interrupt Clear' register)
4/52 Checking commit 632d45ea595a (mainstone: Make providing flash images 
non-mandatory)
5/52 Checking commit f74d35c5333c (z2: Make providing flash images 
non-mandatory)
6/52 Checking commit 0f3e06613a01 (target/arm: Flush high bits of sve register 
after AdvSIMD EXT)
7/52 Checking commit 8612c531ec46 (target/arm: Flush high bits of sve register 
after AdvSIMD TBL/TBX)
8/52 Checking commit d0659424278e (target/arm: Flush high bits of sve register 
after AdvSIMD ZIP/UZP/TRN)
9/52 Checking commit 5c7354ee904c (target/arm: Flush high bits of sve register 
after AdvSIMD INS)
10/52 Checking commit 9bac411e47c0 (target/arm: Use bit 55 explicitly for pauth)
11/52 Checking commit d130aa3da5e3 (target/arm: Fix select for 
aa64_va_parameters_both)
12/52 Checking commit 96873ae455c9 (target/arm: Remove ttbr1_valid check from 
get_phys_addr_lpae)
13/52 Checking commit 86710146cf65 (target/arm: Split out 
aa64_va_parameter_tbi, aa64_va_parameter_tbid)
14/52 Checking commit 1d8dc7edd6c5 (target/arm: Add _aa32_ to isar_feature 
functions testing 32-bit ID registers)
15/52 Checking commit 763de400373e (target/arm: Check aa32_pan in 
take_aarch32_exception(), not aa64_pan)
16/52 Checking commit d46a14b37466 (target/arm: Add isar_feature_any_fp16 and 
document naming/usage conventions)
17/52 Checking commit ee5443024470 (target/arm: Define and use any_predinv 
isar_feature test)
18/52 Checking commit 48acad969806 (target/arm: Factor out PMU register 
definitions)
19/52 Checking commit 43e317fd0578 (target/arm: Add and use FIELD definitions 
for ID_AA64DFR0_EL1)
20/52 Checking commit 5915825b6868 (target/arm: Use FIELD macros for clearing 
ID_DFR0 PERFMON field)
21/52 Checking commit 579bcd1920e3 (target/arm: Define an aa32_pmu_8_1 isar 
feature test function)
22/52 Checking commit 6e40c832d7b5 (target/arm: Add _aa64_ and _any_ versions 
of pmu_8_1 isar checks)
23/52 Checking commit 258a687bbb1b (target/arm: Stop assuming DBGDIDR always 
exists)
24/52 Checking commit a269f0bcec86 (target/arm: Move DBGDIDR into 
ARMISARegisters)
25/52 Checking commit 80bc2137d871 (target/arm: Read debug-related ID registers 
from KVM)
26/52 Checking commit 0774d69c2659 (target/arm: Implement ARMv8.1-PMU extension)
27/52 Checking commit bff845e81d53 (target/arm: Implement ARMv8.4-PMU extension)
28/52 Checking commit 3bb509d54ba8 (target/arm: Provide ARMv8.4-PMU in '-cpu 
max')
29/52 Checking commit 653df0ef05c5 (target/arm: Correct definition of PMCRDP)
30/52 Checking commit c8f037c43173 (target/arm: Correct handling of PMCR_EL0.LC 
bit)
31/52 Checking commit 64cfed1bc429 (target/arm: Test correct register in 
aa32_pan and aa32_ats1e1 checks)
32/52 Checking commit e2fa0930d195 (target/arm: Use isar_feature function for 
testing AA32HPD feature)
33/52 Checking commit d23b72bea5c1 (target/arm: Use FIELD_EX32 for testing 
32-bit fields)
34/52 Checking commit 50cb69482d1a (target/arm: Correctly implement ACTLR2, 
HACTLR2)
35/52 Checking commit 2d78af34a45e (hw: usb: hcd-ohci: Move OHCISysBusState and 
TYPE_SYSBUS_OHCI to include file)
36/52 Checking commit fa553eb6a5bd (hcd-ehci: Introduce "companion-enable" 
sysbus property)
37/52 Checking commit c1ae8a04cda4 (arm: allwinner: Wire up USB ports)
38/52 Checking commit a05bc4b1d564 (target/arm: Vectorize USHL and SSHL)
ERROR: trailing statements should be on next line
#163: FILE: target/arm/translate.c:3578:
+            case 2: gen_ushl_i32(var, var, shift); break;

ERROR: trailing statements should be on next line
#170: FILE: target/arm/translate.c:3584:
+            case 2: gen_sshl_i32(var, var, shift); break;

total: 2 errors, 0 warnings, 569 lines checked

Patch 38/52 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

39/52 Checking commit 70b0557324bd (target/arm: Convert PMUL.8 to gvec)
40/52 Checking commit 905fba66ed2f (target/arm: Convert PMULL.64 to gvec)
41/52 Checking commit 4d6c39043cd2 (target/arm: Convert PMULL.8 to gvec)
42/52 Checking commit aa6e40ef345f (xilinx_spips: Correct the number of dummy 
cycles for the FAST_READ_4 cmd)
43/52 Checking commit 96f769429459 (sh4: Fix PCI ISA IO memory subregion)
44/52 Checking commit bef8c865a7b0 (target/arm: Rename 
isar_feature_aa32_simd_r32)
45/52 Checking commit 15e4e4a3e709 (target/arm: Use isar_feature_aa32_simd_r32 
more places)
46/52 Checking commit 3429e7414f4e (target/arm: Set MVFR0.FPSP for ARMv5 cpus)
47/52 Checking commit 30aecdc707f3 (target/arm: Add isar_feature_aa32_simd_r16)
48/52 Checking commit 2b38215108db (target/arm: Rename 
isar_feature_aa32_fpdp_v2)
49/52 Checking commit d0860b2fe83f (target/arm: Add isar_feature_aa32_{fpsp_v2, 
fpsp_v3, fpdp_v3})
50/52 Checking commit c568474bde1f (target/arm: Perform fpdp_v2 check first)
51/52 Checking commit 27b2141c3dda (target/arm: Replace ARM_FEATURE_VFP3 checks 
with fp{sp, dp}_v3)
52/52 Checking commit ca0e9f4bb0ea (target/arm: Add missing checks for fpsp_v2)
=== OUTPUT END ===

Test command exited with code: 1


The full log is available at
http://patchew.org/logs/address@hidden/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [https://patchew.org/].
Please send your feedback to address@hidden