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[PULL 44/52] target/arm: Rename isar_feature_aa32_simd_r32
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From: |
Peter Maydell |
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Subject: |
[PULL 44/52] target/arm: Rename isar_feature_aa32_simd_r32 |
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Date: |
Fri, 21 Feb 2020 13:07:32 +0000 |
From: Richard Henderson <address@hidden>
The old name, isar_feature_aa32_fp_d32, does not reflect
the MVFR0 field name, SIMDReg.
Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
[PMM: wrapped one long line]
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/cpu.h | 2 +-
target/arm/translate-vfp.inc.c | 53 +++++++++++++++++-----------------
2 files changed, 28 insertions(+), 27 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index b4c83a1cb52..65171cb30ee 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3450,7 +3450,7 @@ static inline bool isar_feature_aa32_fp16_arith(const
ARMISARegisters *id)
return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) == 1;
}
-static inline bool isar_feature_aa32_fp_d32(const ARMISARegisters *id)
+static inline bool isar_feature_aa32_simd_r32(const ARMISARegisters *id)
{
/* Return true if D16-D31 are implemented */
return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) >= 2;
diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c
index bf90ac0e5b7..ba46e2557a1 100644
--- a/target/arm/translate-vfp.inc.c
+++ b/target/arm/translate-vfp.inc.c
@@ -201,7 +201,7 @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a)
}
/* UNDEF accesses to D16-D31 if they don't exist */
- if (dp && !dc_isar_feature(aa32_fp_d32, s) &&
+ if (dp && !dc_isar_feature(aa32_simd_r32, s) &&
((a->vm | a->vn | a->vd) & 0x10)) {
return false;
}
@@ -334,7 +334,7 @@ static bool trans_VMINMAXNM(DisasContext *s, arg_VMINMAXNM
*a)
}
/* UNDEF accesses to D16-D31 if they don't exist */
- if (dp && !dc_isar_feature(aa32_fp_d32, s) &&
+ if (dp && !dc_isar_feature(aa32_simd_r32, s) &&
((a->vm | a->vn | a->vd) & 0x10)) {
return false;
}
@@ -420,7 +420,7 @@ static bool trans_VRINT(DisasContext *s, arg_VRINT *a)
}
/* UNDEF accesses to D16-D31 if they don't exist */
- if (dp && !dc_isar_feature(aa32_fp_d32, s) &&
+ if (dp && !dc_isar_feature(aa32_simd_r32, s) &&
((a->vm | a->vd) & 0x10)) {
return false;
}
@@ -484,7 +484,7 @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a)
}
/* UNDEF accesses to D16-D31 if they don't exist */
- if (dp && !dc_isar_feature(aa32_fp_d32, s) && (a->vm & 0x10)) {
+ if (dp && !dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) {
return false;
}
@@ -556,7 +556,7 @@ static bool trans_VMOV_to_gp(DisasContext *s,
arg_VMOV_to_gp *a)
uint32_t offset;
/* UNDEF accesses to D16-D31 if they don't exist */
- if (!dc_isar_feature(aa32_fp_d32, s) && (a->vn & 0x10)) {
+ if (!dc_isar_feature(aa32_simd_r32, s) && (a->vn & 0x10)) {
return false;
}
@@ -615,7 +615,7 @@ static bool trans_VMOV_from_gp(DisasContext *s,
arg_VMOV_from_gp *a)
uint32_t offset;
/* UNDEF accesses to D16-D31 if they don't exist */
- if (!dc_isar_feature(aa32_fp_d32, s) && (a->vn & 0x10)) {
+ if (!dc_isar_feature(aa32_simd_r32, s) && (a->vn & 0x10)) {
return false;
}
@@ -662,7 +662,7 @@ static bool trans_VDUP(DisasContext *s, arg_VDUP *a)
}
/* UNDEF accesses to D16-D31 if they don't exist */
- if (!dc_isar_feature(aa32_fp_d32, s) && (a->vn & 0x10)) {
+ if (!dc_isar_feature(aa32_simd_r32, s) && (a->vn & 0x10)) {
return false;
}
@@ -912,7 +912,7 @@ static bool trans_VMOV_64_dp(DisasContext *s,
arg_VMOV_64_dp *a)
*/
/* UNDEF accesses to D16-D31 if they don't exist */
- if (!dc_isar_feature(aa32_fp_d32, s) && (a->vm & 0x10)) {
+ if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) {
return false;
}
@@ -978,7 +978,7 @@ static bool trans_VLDR_VSTR_dp(DisasContext *s,
arg_VLDR_VSTR_dp *a)
TCGv_i64 tmp;
/* UNDEF accesses to D16-D31 if they don't exist */
- if (!dc_isar_feature(aa32_fp_d32, s) && (a->vd & 0x10)) {
+ if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) {
return false;
}
@@ -1101,7 +1101,7 @@ static bool trans_VLDM_VSTM_dp(DisasContext *s,
arg_VLDM_VSTM_dp *a)
}
/* UNDEF accesses to D16-D31 if they don't exist */
- if (!dc_isar_feature(aa32_fp_d32, s) && (a->vd + n) > 16) {
+ if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd + n) > 16) {
return false;
}
@@ -1309,7 +1309,7 @@ static bool do_vfp_3op_dp(DisasContext *s, VFPGen3OpDPFn
*fn,
TCGv_ptr fpst;
/* UNDEF accesses to D16-D31 if they don't exist */
- if (!dc_isar_feature(aa32_fp_d32, s) && ((vd | vn | vm) & 0x10)) {
+ if (!dc_isar_feature(aa32_simd_r32, s) && ((vd | vn | vm) & 0x10)) {
return false;
}
@@ -1458,7 +1458,7 @@ static bool do_vfp_2op_dp(DisasContext *s, VFPGen2OpDPFn
*fn, int vd, int vm)
TCGv_i64 f0, fd;
/* UNDEF accesses to D16-D31 if they don't exist */
- if (!dc_isar_feature(aa32_fp_d32, s) && ((vd | vm) & 0x10)) {
+ if (!dc_isar_feature(aa32_simd_r32, s) && ((vd | vm) & 0x10)) {
return false;
}
@@ -1822,7 +1822,8 @@ static bool trans_VFM_dp(DisasContext *s, arg_VFM_dp *a)
}
/* UNDEF accesses to D16-D31 if they don't exist. */
- if (!dc_isar_feature(aa32_fp_d32, s) && ((a->vd | a->vn | a->vm) & 0x10)) {
+ if (!dc_isar_feature(aa32_simd_r32, s) &&
+ ((a->vd | a->vn | a->vm) & 0x10)) {
return false;
}
@@ -1921,7 +1922,7 @@ static bool trans_VMOV_imm_dp(DisasContext *s,
arg_VMOV_imm_dp *a)
vd = a->vd;
/* UNDEF accesses to D16-D31 if they don't exist. */
- if (!dc_isar_feature(aa32_fp_d32, s) && (vd & 0x10)) {
+ if (!dc_isar_feature(aa32_simd_r32, s) && (vd & 0x10)) {
return false;
}
@@ -2065,7 +2066,7 @@ static bool trans_VCMP_dp(DisasContext *s, arg_VCMP_dp *a)
}
/* UNDEF accesses to D16-D31 if they don't exist. */
- if (!dc_isar_feature(aa32_fp_d32, s) && ((a->vd | a->vm) & 0x10)) {
+ if (!dc_isar_feature(aa32_simd_r32, s) && ((a->vd | a->vm) & 0x10)) {
return false;
}
@@ -2138,7 +2139,7 @@ static bool trans_VCVT_f64_f16(DisasContext *s,
arg_VCVT_f64_f16 *a)
}
/* UNDEF accesses to D16-D31 if they don't exist. */
- if (!dc_isar_feature(aa32_fp_d32, s) && (a->vd & 0x10)) {
+ if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) {
return false;
}
@@ -2204,7 +2205,7 @@ static bool trans_VCVT_f16_f64(DisasContext *s,
arg_VCVT_f16_f64 *a)
}
/* UNDEF accesses to D16-D31 if they don't exist. */
- if (!dc_isar_feature(aa32_fp_d32, s) && (a->vm & 0x10)) {
+ if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) {
return false;
}
@@ -2264,7 +2265,7 @@ static bool trans_VRINTR_dp(DisasContext *s,
arg_VRINTR_dp *a)
}
/* UNDEF accesses to D16-D31 if they don't exist. */
- if (!dc_isar_feature(aa32_fp_d32, s) && ((a->vd | a->vm) & 0x10)) {
+ if (!dc_isar_feature(aa32_simd_r32, s) && ((a->vd | a->vm) & 0x10)) {
return false;
}
@@ -2325,7 +2326,7 @@ static bool trans_VRINTZ_dp(DisasContext *s,
arg_VRINTZ_dp *a)
}
/* UNDEF accesses to D16-D31 if they don't exist. */
- if (!dc_isar_feature(aa32_fp_d32, s) && ((a->vd | a->vm) & 0x10)) {
+ if (!dc_isar_feature(aa32_simd_r32, s) && ((a->vd | a->vm) & 0x10)) {
return false;
}
@@ -2384,7 +2385,7 @@ static bool trans_VRINTX_dp(DisasContext *s,
arg_VRINTX_dp *a)
}
/* UNDEF accesses to D16-D31 if they don't exist. */
- if (!dc_isar_feature(aa32_fp_d32, s) && ((a->vd | a->vm) & 0x10)) {
+ if (!dc_isar_feature(aa32_simd_r32, s) && ((a->vd | a->vm) & 0x10)) {
return false;
}
@@ -2412,7 +2413,7 @@ static bool trans_VCVT_sp(DisasContext *s, arg_VCVT_sp *a)
TCGv_i32 vm;
/* UNDEF accesses to D16-D31 if they don't exist. */
- if (!dc_isar_feature(aa32_fp_d32, s) && (a->vd & 0x10)) {
+ if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) {
return false;
}
@@ -2440,7 +2441,7 @@ static bool trans_VCVT_dp(DisasContext *s, arg_VCVT_dp *a)
TCGv_i32 vd;
/* UNDEF accesses to D16-D31 if they don't exist. */
- if (!dc_isar_feature(aa32_fp_d32, s) && (a->vm & 0x10)) {
+ if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) {
return false;
}
@@ -2494,7 +2495,7 @@ static bool trans_VCVT_int_dp(DisasContext *s,
arg_VCVT_int_dp *a)
TCGv_ptr fpst;
/* UNDEF accesses to D16-D31 if they don't exist. */
- if (!dc_isar_feature(aa32_fp_d32, s) && (a->vd & 0x10)) {
+ if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) {
return false;
}
@@ -2534,7 +2535,7 @@ static bool trans_VJCVT(DisasContext *s, arg_VJCVT *a)
}
/* UNDEF accesses to D16-D31 if they don't exist. */
- if (!dc_isar_feature(aa32_fp_d32, s) && (a->vm & 0x10)) {
+ if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) {
return false;
}
@@ -2627,7 +2628,7 @@ static bool trans_VCVT_fix_dp(DisasContext *s,
arg_VCVT_fix_dp *a)
}
/* UNDEF accesses to D16-D31 if they don't exist. */
- if (!dc_isar_feature(aa32_fp_d32, s) && (a->vd & 0x10)) {
+ if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) {
return false;
}
@@ -2723,7 +2724,7 @@ static bool trans_VCVT_dp_int(DisasContext *s,
arg_VCVT_dp_int *a)
TCGv_ptr fpst;
/* UNDEF accesses to D16-D31 if they don't exist. */
- if (!dc_isar_feature(aa32_fp_d32, s) && (a->vm & 0x10)) {
+ if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) {
return false;
}
--
2.20.1
- [PULL 31/52] target/arm: Test correct register in aa32_pan and aa32_ats1e1 checks, (continued)
- [PULL 31/52] target/arm: Test correct register in aa32_pan and aa32_ats1e1 checks, Peter Maydell, 2020/02/21
- [PULL 34/52] target/arm: Correctly implement ACTLR2, HACTLR2, Peter Maydell, 2020/02/21
- [PULL 35/52] hw: usb: hcd-ohci: Move OHCISysBusState and TYPE_SYSBUS_OHCI to include file, Peter Maydell, 2020/02/21
- [PULL 37/52] arm: allwinner: Wire up USB ports, Peter Maydell, 2020/02/21
- [PULL 36/52] hcd-ehci: Introduce "companion-enable" sysbus property, Peter Maydell, 2020/02/21
- [PULL 39/52] target/arm: Convert PMUL.8 to gvec, Peter Maydell, 2020/02/21
- [PULL 42/52] xilinx_spips: Correct the number of dummy cycles for the FAST_READ_4 cmd, Peter Maydell, 2020/02/21
- [PULL 40/52] target/arm: Convert PMULL.64 to gvec, Peter Maydell, 2020/02/21
- [PULL 38/52] target/arm: Vectorize USHL and SSHL, Peter Maydell, 2020/02/21
- [PULL 41/52] target/arm: Convert PMULL.8 to gvec, Peter Maydell, 2020/02/21
- [PULL 44/52] target/arm: Rename isar_feature_aa32_simd_r32,
Peter Maydell <=
- [PULL 45/52] target/arm: Use isar_feature_aa32_simd_r32 more places, Peter Maydell, 2020/02/21
- [PULL 46/52] target/arm: Set MVFR0.FPSP for ARMv5 cpus, Peter Maydell, 2020/02/21
- [PULL 49/52] target/arm: Add isar_feature_aa32_{fpsp_v2, fpsp_v3, fpdp_v3}, Peter Maydell, 2020/02/21
- [PULL 48/52] target/arm: Rename isar_feature_aa32_fpdp_v2, Peter Maydell, 2020/02/21
- [PULL 43/52] sh4: Fix PCI ISA IO memory subregion, Peter Maydell, 2020/02/21
- [PULL 47/52] target/arm: Add isar_feature_aa32_simd_r16, Peter Maydell, 2020/02/21
- [PULL 51/52] target/arm: Replace ARM_FEATURE_VFP3 checks with fp{sp, dp}_v3, Peter Maydell, 2020/02/21
- [PULL 50/52] target/arm: Perform fpdp_v2 check first, Peter Maydell, 2020/02/21
- [PULL 52/52] target/arm: Add missing checks for fpsp_v2, Peter Maydell, 2020/02/21
- Re: [PULL 00/52] target-arm queue, no-reply, 2020/02/21